Patents Examined by Sun Mi Kim King
  • Patent number: 10639747
    Abstract: A method of manufacturing a light emitting element includes: providing a wafer that includes a substrate having a first principal face and a second principal face, a dielectric multilayer film disposed on the first principal face, and a semiconductor structure disposed on the second principal face; forming modified regions in the substrate by focusing a laser beam inside the substrate via the dielectric multilayer film, and allowing cracks to form from the modified regions to the dielectric multilayer film; subsequent to forming the modified regions in the substrate, removing regions of the dielectric multilayer film that contain cracks; and cleaving the wafer along regions where cracks were formed in the substrate.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: May 5, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Naoto Inoue, Yoshitaka Sumitomo
  • Patent number: 10640368
    Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit electrically connected to the gas-sensing device, is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, wherein the platinum (Pt) layer directly contacts the top surface of the tungsten layer.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: May 5, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Fan Hu, Chia-Wei Lee, Chang-Sheng Hsu, Weng-Yi Chen
  • Patent number: 10566455
    Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: February 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masami Jintyou, Yasutaka Nakazawa, Yukinori Shima
  • Patent number: 10559695
    Abstract: To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10546974
    Abstract: Disclosed are a light-emitting device, a method of fabricating the same, a light-emitting device package, and a lighting system. The light-emitting device includes a first-conductivity-type semiconductor layer, an active layer disposed on the first-conductivity-type semiconductor layer and including a quantum well having a composition of InxGa1-xN (0<x<1) and a quantum barrier having a composition of InyGa1-yN (0?y<1), and a second-conductivity-type semiconductor layer disposed on the active layer. The active layer includes a first quantum well disposed on the first-conductivity-type semiconductor layer, a first quantum barrier disposed on the first quantum well, a second quantum well disposed on the first quantum barrier, and a second quantum barrier disposed on the second quantum well.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: January 28, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Hyun Oh Kang
  • Patent number: 10522666
    Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 31, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
  • Patent number: 10515678
    Abstract: A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: December 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Boyoung Seo, Seongui Seo, Gwanhyeob Koh, Yongkyu Lee
  • Patent number: 10504894
    Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: December 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung Hyun Song, Yoon Suk Kim, Kyu Baik Chang, Ui Hui Kwon, Yo Han Kim, Jong Chol Kim, Chang Wook Jeong
  • Patent number: 10475651
    Abstract: A method for patterning a piece of carbon nanomaterial. The method comprises generating a first light pulse sequence with first light pulse sequence property values, the first light pulse sequence comprising at least one light pulse and exposing a first area of the piece of carbon nanomaterial to said first light pulse sequence in a first process environment having a first oxygen content, without exposing at least part of the piece of carbon nanomaterial to said first light pulse sequence. In this way, the method comprises oxidizing locally, in the first area, at least some carbon atoms of the piece of carbon nanomaterial in such a way that at most 10% of the carbon atoms of the first area are removed from the first area; thereby patterning the first area of the piece of carbon nanomaterial. In addition a processed piece of carbon nanomaterial.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: November 12, 2019
    Assignee: Jyv¿skyl¿nYliopisto
    Inventors: Mika Pettersson, Andreas Johansson, Jukka Aumanen, Pasi Myllyperkiö, Juha Koivistoinen
  • Patent number: 10461227
    Abstract: A method for manufacturing a light emitting device comprises a package preparation step of preparing a package having a recess in which a light emitting element is locatable, wherein the package includes a projection extending from an upper surface of the package, the projection at least partially surrounding the recess, a sealing resin forming step of filling said recess in which said light emitting element is located with a sealing resin, and providing said sealing resin higher than the height of said package, and a sealing resin cutting step of cutting the sealing resin such that an upper surface of the sealing resin is at a height that is substantially the same as a height of the upper surface of the package.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 29, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Yusuke Shimada, Motoaki Mando
  • Patent number: 10438870
    Abstract: A semiconductor device packaging assembly includes a lead frame strip having a plurality of unit lead frames. Each of the unit lead frames includes a periphery structure connected to adjacent ones of the unit lead frames, a die paddle inside of the periphery structure, a plurality of leads extending between the periphery structure and the die paddle, and a molding compound channel in the periphery structure configured to guide liquefied molding material onto the periphery structure.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies AG
    Inventors: Boon Teik Tee, Tiam Sen Ong
  • Patent number: 10438906
    Abstract: A reference circuit includes an integrated circuit (IC) formed on a semiconductor substrate including a first spiral inductor and a second spiral inductor. The first spiral inductor is formed from a first metal layer over the substrate. The second spiral inductor is formed from a second metal layer. The second spiral inductor is offset from the first spiral inductor and includes a first portion overlapping the first spiral inductor. A first capacitor includes a first terminal coupled to receive a radio frequency (RF) signal and a second terminal coupled to a first terminal of the first spiral inductor, and second capacitor includes a first terminal coupled to a second terminal of the first spiral inductor.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: October 8, 2019
    Assignee: NXP USA, INC.
    Inventors: Joseph Staudinger, James Krehbiel
  • Patent number: 10403763
    Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 3, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Junichiro Sakata, Takuya Hirohashi, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga
  • Patent number: 10403735
    Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Kyun An, Dong Hyun Im
  • Patent number: 10396152
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10332979
    Abstract: Semiconductor devices including semiconductor junctions and semiconductor field effect transistors that exploit the straining of semiconductor materials to improve device performance are provided. Also described are methods for making semiconductor structures. Dislocation defect-free epitaxial grown structures that are embedded into a semiconductor base are provided. The epitaxial structures can extend beyond the surface of the semiconductor base and terminate at a faceted structure. The epitaxial structures are formed using a multilayer growth process that provides for continuous transitions between adjacent layers.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: June 25, 2019
    Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATION
    Inventors: Runling Li, Haifeng Zhou
  • Patent number: 10326025
    Abstract: To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Patent number: 10319759
    Abstract: An image pickup element mounting substrate includes: a frame body composed of an insulating layer, a through hole being defined by an internal periphery of the frame body; an electronic component mounted on a lower surface side of the frame body; and a flat plate which is disposed on a lower surface of the frame body and covers an opening of the through hole while being partly kept in out-of-contact with the electronic component, the flat plate including an image pickup element mounting section at a part of an upper surface thereof which part is surrounded by the frame body, a lower surface of the electronic component being located above a level of a lower surface of the flat plate.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: June 11, 2019
    Assignee: Kyocera Corporation
    Inventors: Takuji Okamura, Akihiko Funahashi
  • Patent number: 10312383
    Abstract: The present invention applies to the technical field of photoelectric detectors and provides a high-frequency photoelectric detector encapsulation base can-packaged by using a multi-layer ceramic, comprising a laminated multi-layer ceramic substrate, wherein the multi-layer ceramic substrate is welded with pins at a bottom and provided with a metal ring at a top; an upper surface and a lower surface of each layer of the ceramic substrate are both plated with a conductive metal layer; circuit connection holes are distributed in each layer of the ceramic substrate; the upper surface of the multi-layer ceramic substrate is provided with two power contacts and two differential signal contacts; and the power contacts and the differential signal contacts penetrate through each layer of the ceramic substrate to be connected to the corresponding pins.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 4, 2019
    Assignee: WUHAN TELECOMMUNICATION DEVICES CO., LTD.
    Inventors: Zhicheng Su, Tuquan Chen, Xuyu Song
  • Patent number: 10304812
    Abstract: An optoelectronic device including a first integrated circuit that includes:—a substrate, having first and second opposite surfaces; and—groups of sets of light-emitting diodes resting on the first surface. The integrated circuit also includes:—in the substrate, first side elements for electrically insulating portions of the substrate around each set; and—for each group on the second surface, at least one first conductive contact, connected to the first terminal of the group, and one second conductive contact, connected to the second terminal of the group. The device includes a second integrated circuit containing:—third and fourth opposite surfaces; and—third conductive contacts, located on the third surface and electrically connected to the first and second conductive contacts. The first integrated circuit is attached onto the third surface of the second integrated circuit.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 28, 2019
    Assignee: Aledia
    Inventors: Frédéric Mercier, Philipe Gilet, Xavier Hugon