Patents Examined by Suresh Memula
  • Patent number: 11074380
    Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The method can include transmitting the configuration data to the host server computer in response to the second request so that the configurable hardware is configured with the host logic and the application logic.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: July 27, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Patent number: 11075547
    Abstract: A coil module is disposed inside an electronic apparatus and receives prescribed power. The coil module includes a loop coil, a plate-like magnetic body that is disposed on the loop coil, and a conductive member that has prescribed conductivity and is disposed parallel with the plate-like magnetic body and on a surface, opposite to a surface on which the loop coil is disposed, of the magnetic body. The conductive member projects outward relative to at least a portion of a circumferential surface of the magnetic body.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: July 27, 2021
    Assignee: Sovereign Peak Ventures, LLC
    Inventors: Takanori Hirobe, Yoshio Koyanagi, Hiroyuki Uejima
  • Patent number: 11068636
    Abstract: A design method for a semiconductor package including a first chip, a second chip, a 2.5 dimensional (2.5D) interposer, a package substrate, and a board includes generating a layout including the 2.5D interposer on the package substrate and the first and second chips individually arranged on the 2.5D interposer, based on design information; analyzing signal integrity and power integrity between the first and second chips from the layout; analyzing signal integrity or power integrity between the first chip and at least one third chip on the board from the layout; and determining whether to modify the layout based on the analysis results.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 20, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonjae Hwang, Sungwook Moon
  • Patent number: 11068637
    Abstract: Systems and methods for context aware circuit design are described herein. A method includes: identifying at least one cell to be designed into a circuit; identifying at least one context parameter having an impact to layout dependent effect of the circuit; generating, for each cell and for each context parameter, a plurality of abutment environments associated with the cell; estimating, for each cell and each context parameter, a sensitivity of at least one electrical property of the cell to the context parameter by generating a plurality of electrical property values of the cell under the plurality of abutment environments; and determining whether each context parameter is a key context parameter for a static analysis of the circuit, based on the sensitivity of the at least one electrical property of each cell and based on at least one predetermined threshold.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: July 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Chung Hsu, Yen-Pin Chen, Sung-Yen Yeh, Jerry Chang-Jui Kao, Chung-Hsing Wang
  • Patent number: 11055464
    Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chi-Ming Tsai
  • Patent number: 11057026
    Abstract: A semi-dynamic flip-flop includes a semiconductor substrate, first through fourth power rails, and at least one clock gate line. The first through fourth power rails are disposed on the semiconductor substrate, extend in a first direction, and are arranged sequentially in a second direction substantially perpendicular to the first direction. The at least one clock gate line is disposed on the semiconductor substrate, and extends in the second direction to pass through at least two regions among a first region between the first power rail and the second power rail, a second region between the second power rail and the third power rail, and a third region between the third power rail and the fourth power rail. The at least one clock gate line receives an input clock signal.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongkyu Ryu, Minsu Kim, Ahreum Kim, Daeseong Lee, Hyun Lee
  • Patent number: 11048851
    Abstract: A stretchable electronics generating apparatus and layout method thereof are provided. The layout method includes: establishing a layout database, wherein the layout database recodes a plurality of layout selection information respectively corresponding to a plurality of strain/stress information; detecting a layout target area to obtain a strain/stress distribution status of the layout target area; generating a wire routing information according to the strain/stress distribution status based on the layout database; and transporting the wire routing information to a manufacture device of the conductive wires for disposing a plurality of physical conductive wires on the layout target area by the manufacture device.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: June 29, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Ta Pan, Hung-Hsien Ko, Cheng-Chung Lee, Chang-Ying Chen, Wen-Yung Yeh
  • Patent number: 11043854
    Abstract: In accordance with an embodiment, a wireless power transmitter includes a charging surface, a transmitting antenna configured to generate an electromagnetic field extending above the charging surface, a sensing array disposed between the transmitting antenna and the charging surface, and a controller coupled to the sensing array. The sensing array includes a plurality of sensors. Each sensor of the plurality of sensors is configured to generate a respective signal indicative of a strength of the electromagnetic field. The controller is configured to detect a presence of a metallic object, other than a receiving antenna of a power receiver, in the electromagnetic field based on the respective signal generated by one or more sensors of the plurality of sensors.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: June 22, 2021
    Assignee: Spark Connected LLC
    Inventors: Petru Emanuel Stingu, Kenneth Moore
  • Patent number: 11042981
    Abstract: In one embodiment, a computing system may access design data of a printed circuit board to be produced by a first manufacturing process. The system may analyze the design data of the printed circuit board using a machine-learning model, wherein the machine-learning model is trained based on X-ray inspection data associated with the first manufacturing process. The system may automatically determine one or more corrections for the design data of the printed circuit board based on the analysis result by the machine-learning model.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: June 22, 2021
    Assignee: SVXR, Inc.
    Inventors: David Lewis Adler, Freddie Erich Babian, Scott Joseph Jewler
  • Patent number: 11031789
    Abstract: A battery pack management system includes a controller, an isolation unit, a plurality of battery pack management units, and a plurality of battery packs. The plurality of battery pack management units are connected in series by a first daisy chain, and the plurality of battery pack management units are also connected in series by a second daisy chain. The first daisy chain transmits sampled data that is collected by the battery pack management units from corresponding battery packs and transmits control instructions of the controller. The second daisy chain transmits a failure prompt signal which is generated by a battery pack management unit that detects a failure. A first battery pack management unit and a last battery pack management unit of the plurality of battery pack management units connected in series are connected to the controller through the isolation unit.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 8, 2021
    Assignee: Contemporary Amperex Technology Co., Limited
    Inventors: Fupeng Cai, Fuming Ye, Qiandeng Li, Changjian Liu
  • Patent number: 11022894
    Abstract: Several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift, tilt of a Bossung curve of a portion of a design layout used in a patterning process for imaging that portion onto a substrate using a lithographic apparatus. The methods include determining or adjusting one or more characteristics of one or more assist features using the one or more rules based on one or more parameters selected from a group consisting of: one or more characteristics of one or more design features in the portion, one or more characteristics of the patterning process, one or more characteristics of the lithographic apparatus, and/or a combination selected from the foregoing.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: June 1, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Duan-Fu Stephen Hsu, Kurt E. Wampler
  • Patent number: 11022566
    Abstract: There is provided a system and method of examination of a semiconductor specimen using an examination recipe. The method includes obtaining a registered image pair, for each design-based structural element associated with a given layer, calculating an edge attribute, using a trained classifier to determine a class of the design-based structural element, and generating a layer score usable to determine validity of the registered image pair. There is also provided a system and method of generating the examination recipe usable for examination of a semiconductor specimen.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 1, 2021
    Assignee: APPLIED MATERIALS ISRAEL LTD.
    Inventors: Dror Alumot, Shalom Elkayam, Shaul Cohen
  • Patent number: 11017147
    Abstract: System and methods for an edge-based camera are disclosed. Semiconductor layout designs are a representation of an integrated circuit that are used to manufacture the integrated circuit. Parts of the layout design, such as points of Interest (POIs), may be subject to analysis with regard to a downstream application, such as hotspot detection. Unlike pixel-based characterizations, POIs are characterized using topological features indicative of quantized values and dimensional features indicative of analog values. For example, an edge may be characterized using a set of relations, which characterizes corners and polygons (including the polygon on which the POI resides and external polygons). In turn, the set of relations may be used to define image representations, including images in different directions relative to the POI (including cardinal and ordinal image). In this way, the topological/dimensional characterization of the POI may be used to analyze the POI in the layout design.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 25, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Hazem Hegazy, Ahmed Hamed Fathi Hamed, Omar Elsewefy
  • Patent number: 11014463
    Abstract: A cable management system for an overhead EVSE employs a lever-latch on the EV connector. A controller and motor mechanism is employed to lower the connector to an ADA compliant position or a pre-established height which is typically four feet. For an overhead system which employs a shuttle which slides along a track, the connector may then be grasped to pull the shuttle to a selected position along the track. The latch is depressible to extend the service cable to the connector so that the connector may be positioned and connected at the EV inlet. When the connector is unlatched from the EV inlet, the latch may be depressed to retract the connector to the pre-established height or ADA position. The latch requires a force of less than 5 lbs. for activation.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: May 25, 2021
    Assignee: Control Module, Inc.
    Inventors: James S. Bianco, David C. Parmelee, David B. Palmer, John Fahy
  • Patent number: 11017140
    Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate and/or support one or more operations and/or techniques for autonomous verification of circuit design for IoT-type devices, which may include, for example, IoT-type devices operating in resource constrained or like environments.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: May 25, 2021
    Assignee: Arm Limited
    Inventors: Andrew Neil Sloss, Christopher Neal Hinds, Hannah Marie Peeler, Gary Dale Carpenter
  • Patent number: 11017139
    Abstract: This application discloses a computing system to select a set of one or more values for control signals internal to multiple circuit designs, generate input stimulus for the circuit designs based, at least in part, on the selected set of values for the control signals, and simulate the circuit designs with the input stimulus, which configures the simulated values of the control signals internal to the circuits designs to the selected set of values. The computing system can perform an equivalence check on the circuit designs using results of the simulation. The computing system can select another set of values for the control signals, and determine that at least the other set of values for the control signals are not realizable during simulation with any input stimulus.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: May 25, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Pritam Roy, Sagar Chaki, Pankaj Chauhan
  • Patent number: 11010521
    Abstract: A method of detecting the relations between the pins of a circuit and a computer program product thereof are provided. The method includes: retrieving a circuit description file describing a circuit; retrieving at least one data pin and at least one clock pin of the circuit; converting the circuit to a cell level; and tracing the circuit in the cell level to identify multiple flip-flops coupled to the clock pin; tracing the circuit in the cell level to identify a target flip-flop coupled to the data pin; and determining whether the data pin is related to the clock pin according to the data signal and the clock signal of the target flip-flop.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 18, 2021
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chia-Ling Hsu, Ting-Hsiung Wang, Meng-Jung Lee, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 11010531
    Abstract: The present invention can determine in advance whether the design RULE is violated by checking the design conditions and design requirements required by the client and the project in the plant engineering stage on the 3D CAD model. The present invention can improve the design quality of plant engineering and minimizing the modification of the drawings occurring during construction by checking whether the various data of the vendor drawings received by the EPC company are accurately reflected to the 3D CAD modeling design.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: May 18, 2021
    Assignee: PLANTASSET TECHNOLOGY INC.
    Inventor: Siyeon Cho
  • Patent number: 11003824
    Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a computer readable representation of said electronic design having at least in one part of said electronic design an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is also received. At least one set of valid states are generated based on said at least one specification. The at least one instrumented netlist is simulated at a behavioral level of said representation of said electronic design at a minimum number of at least one input vector. At least one verification coverage history of said electronic design is generated based in part upon said simulation.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: May 11, 2021
    Assignee: ZIPALOG, INC.
    Inventors: Felicia James, Michael Krasnicki
  • Patent number: 11002791
    Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu