Abstract: Product management and/or prompt defect analysis of a semiconductor device may be carried out without reducing the throughput in assembly and testing. Unique identification information is attached to a plurality of substrates (lead frames) used in manufacturing a semiconductor device (QFP) and to a transport unit for transporting a plurality of substrates, respectively. Identification information (rack ID) of the transport unit and identification information (substrate ID) of the substrate stored into the transport unit are associated with each other. The substrate is taken out from the transport unit set to a loader unit of each manufacturing apparatus and supplied to a processing unit, of the apparatus and in storing the substrate, the processing of which is complete, into a transport unit of an unloader unit of the apparatus, an association between identification information of the transport unit and the identification information of the substrate is checked.

Abstract: The semiconductor device includes a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the semiconductor layer is provided. The semiconductor device includes a first insulating film provided over the lower surface of the semiconductor layer and an inner surface of the via hole. The semiconductor device includes a second insulating film provided over the lower surface of the semiconductor layer and the inner surface of the via hole with the first insulating film interposed between the second insulating film and the semiconductor layer. The semiconductor device includes a device layer including a semiconductor element and provided on the side of the upper surface of the semiconductor layer.

Abstract: Disclosed is a processing apparatus. The processing apparatus includes: a load port in which a conveyance container accommodating a plurality of semiconductor wafers is placed; a dummy wafer storage area in which a conveyance container accommodating a plurality of dummy wafers is placed; a normal-pressure conveyance room in which a first conveyance arm is installed; an equipment that processes the plurality of semiconductor wafers in a state where the semiconductor wafers and the dummy wafers which are conveyed are placed in slots, respectively; and a controller that controls each component of the processing apparatus. The controller classifies the dummy wafers accommodated in the conveyance container into a plurality of groups, and controls the first conveyance arm to preferentially convey the dummy wafers within one of the classified groups to the equipment and, in replacing the dummy wafers, to perform replacement of the dummy wafers group to group as classified.

Abstract: A method for intelligent inline metrology is a provided. A parameter of a workpiece is measured at a first set of inspection sites on the workpiece. A determination is made as to whether a first specification is met using the measurements at the first set of inspection sites. In response to the first specification being met, the parameter is estimated at a second set of inspection sites on the workpiece. In response to the first specification being unmet, the parameter is measured at the second set of inspection sites and a determination is made as to whether a second specification is met using the measurements at the second set of inspection sites. A system for intelligent inline metrology is also provided.

Abstract: An optoelectronic component includes a carrier having an upper side which includes a first subarea and a second subarea, wherein the first subarea and the second subarea have different optical properties, and a method of producing an optoelectronic component includes providing a carrier having an upper side which includes a first subarea and a second subarea, and changing an optical property in the first subarea or in the second subarea.

Abstract: A packaging structure includes a first substrate including a first metal terminal and a first protruding resin portion formed at a first surface; a second substrate including a second metal terminal and a second protruding resin portion formed at a second surface, the second metal terminal being made of the same kind of metal as the first metal terminal; and a sealing portion filled between the first surface of the first substrate and the second surface of the second substrate, the first metal terminal and the second metal terminal being directly bonded with each other, the first protruding resin portion and the second protruding resin portion being directly bonded with each other, each of the first protruding resin portion and the second protruding resin portion being made of a resin material that does not include fillers, and the sealing portion being made of a resin material including fillers.

Abstract: An emission efficiency of a light-emitting device is improved by reducing strains applied to a light-emitting layer. On a sapphire substrate, an n-type contact layer, an nESD layer, an n-type cladding layer, a light-emitting layer, a p-type cladding layer, and a p-type contact layer, are sequentially deposited. The light-emitting layer has a MQW structure in which a layer unit of a well layer, a capping layer, and a barrier layer sequentially deposited is repeatedly deposited. Of the well layers, the In composition ratio of only first well layer is reduced than the In composition ratios of other well layers, and the In composition ratios of the other well layers are equal to each other. The In composition ratio of the first well layer is designed so that the emission wavelength of the first well layer is equal to the emission wavelengths of other well layers.

Abstract: A quantum dot having core-shell structure includes a core formed of ZnOzS1-z, and at least one shell covering the core, and formed of AlxGayIn1-x-yN, wherein at least one of x, y, and z is not zero and is not one.

Abstract: A method for forming nanowires includes forming a plurality of epitaxial layers on a substrate, the layers including alternating material layers with high and low Ge concentration and patterning the plurality of layers to form fins. The fins are etched to form recesses in low Ge concentration layers to form pillars between high Ge concentration layers. The pillars are converted to dielectric pillars. A conformal material is formed in the recesses and on the dielectric pillars. The high Ge concentration layers are condensed to form hexagonal Ge wires with (111) facets. The (111) facets are exposed to form nanowires.

Abstract: A method of detaching a sealing member of a light emitting device which has a substrate, alight emitting element mounted on the substrate and a sealing member that seals the light emitting element, wherein a release layer and/or an air layer is/are provided between the substrate and the sealing member; and the sealing member is detached from the substrate at the release layer and/or the air layer.

Abstract: A semiconductor structure includes a first fin structure having a first strain located on a surface of a first insulator layer portion. The first fin structure includes a first doped silicon germanium alloy fin portion having a first germanium content and a silicon germanium alloy fin portion having a third germanium content. A second fin structure having a second strain is located on a surface of a second insulator layer portion. The second fin structure includes a second doped silicon germanium alloy fin portion having a second germanium content and a silicon germanium alloy fin portion having the third germanium content, wherein the first germanium content differs from the second germanium content and the third germanium content is greater than the first and second germanium contents, and wherein the first strain differs from the second strain.

Abstract: A method for manufacturing a semiconductor device includes forming a trench in at least one dielectric layer; and forming an interconnect structure in the trench, wherein forming the interconnect structure includes forming a first conductive layer on a bottom surface of the trench, and partially filling the trench, and forming a second conductive layer on the first conductive layer, and filling a remaining portion of the trench, wherein the second conductive layer comprises a different material from the first conductive layer, and wherein an amount of the first conductive layer in the trench is controlled so that an aspect ratio of the second conductive layer has a value that is determined to result in columnar grain boundaries in the second conductive layer.

Abstract: There is provided a method of processing a substrate using a block copolymer composed of a first polymer containing an oxygen atom and a second polymer containing no oxygen atom, the method including: coating the block copolymer onto the substrate on which a predetermined pattern is formed; phase-separating the block copolymer into the first polymer and the second polymer; and heating the substrate in a low oxygen atmosphere to selectively remove the first polymer from the phase-separated block copolymer.

Abstract: A method of making an integrated circuit package includes: (a) forcing a circuit layered structure that includes a metal substrate and a circuit pattern, the metal substrate having opposite first and second surfaces, the circuit pattern including at least two spaced apart die contacts that protrude from the first surface of the metal substrate, the metal substrate directly interconnecting the die contacts; (b) bonding first and second terminal contacts of an electronic die to the die contacts, respectively; and (c) forming an insulator layer on the first surface of the metal substrate to encapsulate the die and the die contacts after step (b).

Abstract: An optoelectronic light emission device is provided that includes a gain region of at least one type III-V semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type III-V semiconductor layer has a nanoscale area using nano-cavities. The optoelectronic light emission device is free of defects.

Abstract: Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed.

Abstract: An electronic device comprising at least one electronic component mounted on a support and surrounded by a deformable casing containing a heat-conducting and electrically-insulating liquid, the device comprising a heat dissipation plate that is substantially parallel to the support and spaced apart therefrom, and heat exchange means for heat exchange by conduction between the casing and the plate, the heat-conducting and electrically-insulating liquid being selected and the casing being arranged so that thermal expansion of the oil leads to the casing applying force against the means for heat exchange by conduction.

Abstract: Disclosed is an organic light emitting device. The organic light emitting device includes a first emission unit configured to include a common blue emission material layer which is included in common in a plurality of pixels emitting lights having different wavelength ranges, a second emission unit configured to include a red emission material layer, a green emission material layer, and a blue emission material layer which respectively emit lights having different wavelength ranges, a charge generation layer disposed between the first emission unit and the second emission unit, a first electrode formed as a reflective electrode, and configured to supply an electric charge having a first polarity to the first emission unit and the second emission unit, and a second electrode formed as a semi-transmissive electrode, and configured to supply an electric charge having a second polarity to the first emission unit and the second emission unit.

Abstract: Provided are a semiconductor device including a terminal, a circuit substrate, and a case body and a method for manufacturing the semiconductor device. A semiconductor device (100) includes a terminal (13), a circuit substrate (42), a case body (1), and a positioning component (21). The terminal (13) includes a first end portion (13a), a trunk portion (13b), and a second end portion (13c). The first end portion (13a) of the terminal (13) is secured to the circuit substrate (42). The case body (1) includes a main surface (1s), an opening portion (1op) on a side opposing the main surface (1s), and a groove hole (2) on the main surface (1s) side. A sidewall (5) and a through hole (4) are formed in the groove hole (2). The terminal (13) passes through the through hole (4) toward the main surface (1s) side from the opening portion (1op) side of the case body (1), and the second end portion (13c) protrudes from the main surface (1s) of the case body (1).

Abstract: A two-terminal detector has a back-to-back p/n/p SWIR/MWIR stack structure, which includes P-SWIR absorber, N-SWIR, wide bandgap bather, N-MWIR absorber, and P-MWIR layers, with contacts on the P-MWIR and P-SWIR layers. The junction between the SWIR layers and the junction between the MWIR layers are preferably passivated. The detector stack is preferably arranged such that a negative bias applied to the top of the stack reverse-biases the MWIR junction and forward-biases the SWIR junction, such that the detector collects photocurrent from MWIR radiation. A positive bias forward-biases the MWIR junction and reverse-biases the SWIR junction, such that photocurrent from SWIR radiation is collected. A larger positive bias induces electron avalanche at the SWIR junction, thereby providing detector sensitivity sufficient to provide low light level passive amplified imaging. Detector sensitivity in this mode is preferably sufficient to provide high resolution 3-D eye-safe LADAR imaging.