Patents Examined by Syed I Gheyas
  • Patent number: 11784224
    Abstract: The disclosure provides a lateral bipolar transistor structure with a base layer over a semiconductor buffer, and related methods. A lateral bipolar transistor structure may include an emitter/collector (E/C) layer over an insulator. The E/C layer has a first doping type. A semiconductor buffer is adjacent the insulator. A base layer is on the semiconductor buffer and adjacent the E/C layer, the base layer including a lower surface below the E/C layer and an upper surface above the E/C layer. The base layer has a second doping type opposite the first doping type.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: October 10, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Hong Yu, Jagar Singh, Zhenyu Hu, John J. Pekarik
  • Patent number: 11777019
    Abstract: Disclosed is a semiconductor structure including a device, such as a lateral heterojunction bipolar transistor (HBT), made up of a combination of at least three different semiconductor materials with different bandgap sizes for improved performance. In the device, a base layer of the base region can be positioned laterally between a collector layer of a collector region and an emitter layer of an emitter region and can be physically separated therefrom by buffer layers. The base layer can be made of a narrow bandgap semiconductor material, the collector layer and, optionally, the emitter layer can be made of a wide bandgap semiconductor material, and the buffer layers can be made of a semiconductor material with a bandgap between that of the narrow bandgap semiconductor material and the wide bandgap semiconductor material. Also disclosed herein is a method of forming the structure.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: October 3, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Hong Yu, Vibhor Jain, Judson R. Holt
  • Patent number: 11776995
    Abstract: A transistor is produced by forming a first part of a first region of the transistor in a semiconductor substrate by implanting dopants through an opening in an isolating trench formed at an upper surface of the semiconductor substrate. A second region of the transistor in the opening by epitaxy.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: October 3, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Pascal Chevalier, Gregory Avenier
  • Patent number: 11769803
    Abstract: A semiconductor device includes a substrate; and a fin protruding from the substrate. The fin includes a first material and a second material. The fin includes a lower section, a middle section, and an upper section. The middle section has a smaller width at a middle portion than a width at lower and upper portions of the middle section. A concentration of the second material gradually decreases from the middle portion in upward and downward directions.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: September 26, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sungmin Kim
  • Patent number: 11749727
    Abstract: Structures for a bipolar junction transistor and methods of fabricating a structure for a bipolar junction transistor. The structure includes a first base layer, a second base layer, a first terminal positioned between the first base layer and the second base layer, a second terminal, and a third terminal. The first base layer, the second base layer, and the first terminal are positioned between the second terminal and the third terminal. For example, the first terminal may be positioned in a vertical direction between the first and second base layers.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: September 5, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Shesh Mani Pandey, Hong Yu, Alexander Derrickson
  • Patent number: 11749747
    Abstract: Embodiments of the disclosure provide a bipolar transistor structure with a collector on a polycrystalline isolation layer. A polycrystalline isolation layer may be on a substrate, and a collector layer may be on the polycrystalline isolation layer. The collector layer has a first doping type and includes a polycrystalline semiconductor. A base layer is on the collector layer and has a second doping type opposite the first doping type. An emitter layer is on the base layer and has the first doping type. A material composition of the doped collector region is different from a material composition of the base layer.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: September 5, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Judson R. Holt, Vibhor Jain, Jeffrey B. Johnson, John J. Pekarik
  • Patent number: 11749746
    Abstract: In an aspect, a heterojunction bipolar transistor (HBT) includes a sub-collector disposed on a collector. The collector has a collector contact disposed on the sub-collector and located on a first side of the heterojunction bipolar transistor. The HBT includes an emitter disposed on an emitter cap. The emitter has an emitter contact disposed on the emitter cap and located on a second side of the heterojunction bipolar transistor. The HBT includes a base having a base contact located on the second side of the heterojunction bipolar transistor.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: September 5, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Ranadeep Dutta, Jonghae Kim, Je-Hsiung Lan
  • Patent number: 11728190
    Abstract: A system for thinning a substrate includes a chuck and a first liquid supply unit. The chuck includes a base portion and a frame portion disposed on the base portion, where the substrate is configured to be placed on a carrying surface of the chuck. The first liquid supply unit extends along sidewalls the frame portion and the base portion, an outlet of the first liquid supply unit is disposed next to the carrying surface of the chuck, the first liquid supply unit delivers a first liquid from a bottom of the chuck to the outlet, and the first liquid discharges from the outlet to cover a sidewall of the substrate.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
  • Patent number: 11726387
    Abstract: A trapped-ion quantum logic gate and a method of operating the trapped-ion quantum logic gate are provided. The trapped-ion quantum logic gate includes at least one ion having two internal states and forming a qubit having a qubit transition frequency ?0, a magnetic field gradient, and two microwave fields. Each of the two microwave fields has a respective frequency that is detuned from the qubit transition frequency ?0 by frequency difference ?. The at least one ion has a Rabi frequency ?? due to the two microwave fields and a Rabi frequency ?g due to the magnetic field gradient. The method includes applying the magnetic field gradient and the two microwave fields to the at least one ion such that a quantity ?g/? is in a range between zero and 5×10?2.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: August 15, 2023
    Assignee: Lawrence Livermore National Security, LLC
    Inventor: Robert Tyler Sutherland
  • Patent number: 11721722
    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: August 8, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Man Gu, Jagar Singh, Haiting Wang, Jeffrey Johnson
  • Patent number: 11721726
    Abstract: A semiconductor device including a Horizontal Current Bipolar Transistor (HCBT) and methods of manufacture. The device has a semiconductor substrate of a first conductivity type defining a wafer plane parallel to the semiconductor substrate and has a base region and a collector region forming a first metallurgical junction. The device also has an emitter region forming a second metallurgical junction with the base region. A flat portion of the first metallurgical junction and a flat portion of the second metallurgical junction are substantially parallel to each other and close an acute angle with the wafer plane. At least a portion of the base region comprises silicon-germanium alloy or silicon-germanium-carbon alloy.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: August 8, 2023
    Assignee: University of Zagreb, Faculty of Electrical Engineering and Computing
    Inventors: Tomislav Suligoj, Marko Koricic, Josip Zilak, Zeljko Osrecki
  • Patent number: 11721724
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Nicole K. Thomas, James S. Clarke, Jessica M. Torres, Ravi Pillarisetty, Kanwaljit Singh, Payam Amin, Hubert C. George, Jeanette M. Roberts, Roman Caudillo, David J. Michalak, Zachary R. Yoscovits, Lester Lampert
  • Patent number: 11715788
    Abstract: At least one transistor is arranged on a substrate. A collector layer and a base layer of the transistor compose a collector mesa having a substantially mesa shape and the collector mesa has side faces tilting with respect to the substrate so that the dimension of a top face in a first direction of a plane of the substrate is smaller than the dimension of a bottom face therein. A first insulating film covering the transistor is arranged on the substrate. A first-layer emitter line that extends from an area overlapped with the top face of the collector mesa to areas overlapped with at least part of the tilting side faces of the collector mesa in a plan view is arranged on the first insulating film. A second-layer emitter line and an emitter bump are arranged on the first-layer emitter line.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: August 1, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Kenji Sasaki
  • Patent number: 11716860
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 1, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Hung-Yueh Chen, Wei Chen
  • Patent number: 11710771
    Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: July 25, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Alexander Derrickson, Judson R. Holt, Haiting Wang, Jagar Singh, Vibhor Jain
  • Patent number: 11710776
    Abstract: A bipolar transistor includes a stack of an emitter, a base, and a collector. The base is structured to have a comb shape including fingers oriented in a plane orthogonal to a stacking direction of the stack.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: July 25, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Alexis Gauthier, Edoardo Brezza, Pascal Chevalier
  • Patent number: 11710783
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: July 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Tsung Kuo, Jiech-Fun Lu
  • Patent number: 11700776
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: July 11, 2023
    Assignee: Intel Corporation
    Inventors: Jeanette M. Roberts, Ravi Pillarisetty, David J. Michalak, Zachary R. Yoscovits, James S. Clarke, Van H. Le
  • Patent number: 11688639
    Abstract: A semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor device and a second semiconductor device are formed within a semiconductor wafer and a scribe region between the first semiconductor device and the second semiconductor device is patterned. A singulation process is then utilized within the scribe region to singulate the first semiconductor device from the second semiconductor device. The first semiconductor device and the second semiconductor device are then bonded to a second semiconductor substrate and thinned in order to remove extension regions from the first semiconductor device and the second semiconductor device.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Hung-Pin Chang, Yi-Hsiu Chen, Ku-Feng Yang, Wen-Chih Chiou
  • Patent number: 11680340
    Abstract: Methods and systems for low etch pit density 6 inch semi-insulating gallium arsenide wafers may include a semi-insulating gallium arsenide single crystal wafer having a diameter of 6 inches or greater without intentional dopants for reducing dislocation density, an etch pit density of less than 1000 cm?2, and a resistivity of 1×107 ?-cm or more. The wafer may have an optical absorption of less than 5 cm?1 less than 4 cm?1 or less than 3 cm?1 at 940 nm wavelength. The wafer may have a carrier mobility of 3000 cm2/V-sec or higher. The wafer may have a thickness of 500 ?m or greater. Electronic devices may be formed on a first surface of the wafer. The wafer may have a carrier concentration of 1.1×107 cm?3 or less.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: June 20, 2023
    Assignee: AXT, Inc.
    Inventors: Rajaram Shetty, Weiguo Liu, Morris Young