Abstract: A dual slope A/D converter with a zero compensation circuit includes a single power source, an integrator, and a MOS switch constituting the zero compensation circuit and adapted to apply an output voltage to the noninverting input terminal of an operational amplifier constituting the integrator for a zero compensation duration. The A/D converter further includes an amplifier and a MOS transistor with the same characteristics as those of the MOS switch. The gate and source of the MOS transistor are connected to the noninverting input terminal of the operational amplifier. The amplifier doubles a voltage at the noninverting input terminal of the operational amplifier. A doubled voltage is applied to the drain of the MOS transistor.

Abstract: A system for encoding position information includes a grid of evenly spaced, parallel conductive lines fixed with respect to one of two mechanical parts, the grid being disposed along the line of movement of the parts. Two pairs of interdigitated electrodes capacitively sense the conductive lines of the grid, the electrodes being fixedly disposed on the other mechanical part. Decoding circuitry is responsive to the electrodes for providing relative movement information. The fingers of each electrode are disposed substantially parallel to the grid lines, the capacitance of each electrode with respect to the grid being a function of the proximity of the fingers of that electrode to the grid lines. The decoding circuitry includes first and second latches whose outputs are a function of which electrode of its corresponding pair has the greater capacitance to the grid. The second pair of interdigitated electrodes is offset from the first pair such that its ouput differs from that of the first pair.

Abstract: An A-D converter for providing the general successive rectification algorithm V.sub.out =2.vertline.V.sub.in .vertline.-V.sub.ref is disclosed. One stage of a synchronous parallel converter generally comprises a comparator, and an op amp with V.sub.in as an input to its inverting input, the noninverting input connected to ground, and the output being V.sub.out, with a first capacitor bridging the inputs of the op amp, and a second capacitor of half the capacitance of the first capacitor feeding back from the output of the op amp to its noninverting input. The location and capacitance values of the first and second capacitors perform the amplification function. Switches between the first capacitor and the op amp provide rectification, while a third capacitor between V.sub.ref and the inverting input of the op amp provides the function of subtracting V.sub.ref. Stages are cascaded such that V.sub.out of one stage is the V.sub.in of the next stage. Each stage's V.sub.

Abstract: An apparatus for converting an input voltage into a related output current, is disclosed and generally comprises: a resistance means in series with the voltage input; first and second double output current mirrors, wherein each output of the first double output mirror is connected to a corresponding output of the second double output mirror, and the inputs of the double output current mirrors are connected; and an operational amplifier with the inverting input connected to ground, the noninverting input connected to the resistance means, and the op amp output connected to the inputs of the first and second double output mirrors, wherein first outputs of the first and second double output mirrors are connected to the noninverting input of the operational amplifier, and the second outputs of the first and second double output mirrors are connected to the output current.

Abstract: A successive approximation analog-to-digital converter, of the type which successively compares an analog level represented by binary weighted bits with an analog signal and in response thereto generates a signal indicating whether each successive binary bit should be set or reset, includes a shaft register for counting cycles during the sampling phase and generating signals for controlling the setting and resetting of each bit. Each binary bit cell includes a latch capable of assuming first and second stable states. A first string of field-effect-transistors coupled to the latch and controlled by the shift register receives a first signal indicating that the latch should be reset. A second string of field-effect-transistors coupled to the latch and controlled by the shift register receives a signal indicating that the latch should remain in a set condition.

Abstract: A system for encoding consecutive parallel bytes of source data into an RLL (1,7) output symbol string and decoding an input RLL (1,7) symbol string to produce an output sequence of parallel bytes of data. The system accepts an input sequence of parallel data bytes occurring at a byte rate and provides, in response, the output RLL symbol string at a symbol string rate which is twelve times the byte rate. Similarly, the output byte sequence has a byte rate which is 1/12 of the input RLL symbol string rate. The system performs RLL encoding and decoding at the byte rate, thus eliminating the odd 2/3 f.sub.C source clock required in systems performing RLL coding and decoding functions on a bit-by-bit basis.

Abstract: A digital data signal such as a digitized audio signal is time division multiplexed with a digital dither signal to provide a multiplex signal compound of the digital dither signal and a digital data/dither signal, the latter being an addition of the digital data and dither signals. Then the multiplex signal is converted from digital to analog form by one and the same digital to analog converter. The subsequent removal of the analog dither signal from the analog data/dither signal provides an analog data signal as a replica of the digital data signal. The use of the same converter for the conversion of both dither signal and data/dither signal from digital to analog form makes possible the maximum possible removal of the dither from the analog data/dither signal.

Abstract: A high resolution pipelined digital-to-analog converter is disclosed having at least one switching circuit for conveying charge to at least one conversion capacitor upon receipt of a digital signal during the first half of a clock cycle. Additional switching circuits are provided for transferring the charge from the conversion capacitors to a feedback capacitor during the second half of the clock cycle. Also provided is a circuit for discharging an analog output from, and preventing the charging of, the feedback capacitor during the first half of a succeeding clock cycle. In a preferred embodiment, the pipelined digital-to-analog converter comprises a first plurality of electrical circuits having at least one feedback capacitor and a plurality of conversion capacitors adapted for accepting digital and analog inputs, wherein the ratio of the feedback capacitance to each of the conversion capacitances is substantially independent of the resolution of the converter.

Abstract: In the transmitter of a data communication system using QAM, a plurality of trellis coders with delay units are used for forward error correction. The output of each encoder is modulated using QAM to generate sequential baud signal elements. The redundant data bits generated are distributed between several non-consecutive bauds. Likewise, at the receiver a plurality of distributed convolutional decoders are utilized to decode the received signal element. The distributed trellis decoder is self-synchronizing.

Abstract: A multiple input signal high-speed analog-digital converter circuit for digitizing, by means of an A/D converter, an output signal from a multiplexer which successively delivers multiple input signals applied thereto. Two sample/hold circuits which receive the output signal from the multiplexer repeatedly sample and hold the signal, and a changeover switch keeps one of the sample/hold circuits on hold while the other sample/hold circuit samples the output signal from the multiplexer. While one of the sample/hold circuits is holding the signal, the other sample/hold circuit is sampling another signal so that the A/D conversion time of multiple input signals is capable of being reduced by the sampling time.

Abstract: In the transmitter of a data communication system using QAM, a trellis coder with k-baud delay units is used for forward error correction. The output of the encoder is modulated using QAM to generate sequential baud signal elements. The redundant data bits generated are distributed among several non-consecutive bauds. At the receiver a plurality of distributed convolutional decoders are utilized to decode the received signal element. The distributed trellis decoder is self-synchronizing.

Abstract: In the transmitter of a data communication system using QAM, a plurality of trellis coders with delay units are used for forward error correction. The output of each encoder is modulated using QAM to generate sequential baud signal elements. The redundant data bits generated are distributed among several non-consecutive bauds. At the receiver a distributed convolutional decoder individually addressed having sectioned memory elements is utilized to decode the received signal element. The distributed trellis decoder is self-synchronizing.

Abstract: Code modification circuitry alters the end portion of each block in a sequence of code blocks, and also inserts additional bits at the junction between contiguous blocks. The codes to be processed are run-length limited (RLL) codes having a DC component which is to be removed for certain applications such as magnetic recording. The modification circuitry retains the RLL format. Charge (or the integral of the waveform) accumulated by the sequence of bits of one block is compensated by selecting the sense of charge accumulation in next block to be of opposite sense. This is accomplished by the code modification circuitry using a relatively small set of possible combinations of digital words at the junctions of the blocks.

Abstract: A dichotomizing, high speed analog - digital comprises an input stage for the voltage - current conversion of the analog signal, a reference current source, a sequence of N-1 identical cells in series, each comprising a comparator and current dividers, a terminal cell incorporating a comparator, a digital coder receiving a digital signal from each cell and, optionally, a link positioned between the consecutive cells. The analog signal is processed in the cells entirely in current form, the link means making it possible to isolate the potentials between successive cells.

Abstract: In a data compression system, a digital signal comprising a series of digital samples and a sampling datum indicating the sampling interval of the digital samples are written into a read-write memory (M2). The digital samples and the associated sampling datum are read out of the memory into first and second digital-to-analog converters (DAC1, DAC2), respectively. The output of the first digital-to-analog converter is applied to a variable frequency low-pass filter (5) to remove the components having frequencies higher than a presettable frequency limit value which is variable as a function of the output of the second digital-to-analog converter so that the cut-off frequency is lower than one-half the sampling frequency to eliminate quantum noise.

Abstract: There is provided a method of modulating a data bit series consisting of a first value (e.g., 1) and a second value (e.g., 0) whereby a transition as a state transition is caused so as to satisfy the following conditions of (a) to (d).(a) The transition at the boundary portion of the bit cell which is sandwiched by bits 0.(b) The transition at the central portion of the bit cell of bit 1.(c) Among an even number of the bits of 1 which are sandwiched by bits 0, the transition is inhibited at the central portion of each bit cell of the last two bits of 1 and the transition is caused at the boundary portion of these two bit cells of 1.(d) When at least one bit in a pattern which starts from the two bits of (01) appears at a location next to an even number of the bits of 1 subsequent to bit of 0, the transition is caused at the central portion of the bit cell of bit 0 between these two bits.

Abstract: A data processing system having a central processing unit (CPU) capable of performing binary and decimal arithmetic software instructions is disclosed. Also disclosed is a method and apparatus for speeding conversion of a number in binary format to decimal format by first stripping leading zeroes before the highest order non-zero bit of the binary number, and only allocating enough memory storage bits to hold the resultant decimal number. A multiplexer is used to apply a partial sum during conversion concurrently to both inputs of an adder for doubling.

Abstract: Disclosed is an interpolative A/D converter for converting an over-sampled analog signal into a digital signal without the occurrence of over slope distortions, wherein the difference between the analog input signal and an analog feedback signal derived from the converter output through D/A conversion is integrated, the integrated output is compared with several reference voltages and, after being converted into a digital signal, the comparison result is integrated in a digital manner to complete a digital output signal of the A/D converter.

Abstract: A method of initializing the position of an optical shaft encoder without having to precisely index the encoder with respect to its shaft. The optical encoder includes an optical shutter mounted for rotation with the shaft and light emitters and light detectors associated with the optical shutter for respectively illuminating and detecting a predetermined pattern of code markings formed on the optical shutter. An electrical circuit, such as a suitably programmed microprocessor, is responsive to the status of the light emitters and light detectors for determining the angular position of the optical shutter and shaft relative to the light emitters and detectors from the detected predetermined pattern. The optical shutter is mounted to the shaft in some arbitrary position and the code pattern associated with this position is detected by the electrical circuit.

Abstract: A continuous time domain parallel analog to digital converter is provided for accomplishing the general successive rectification algorithm I.sub.out =2.vertline.I.sub.in .vertline.-I.sub.ref. One stage of the continuous parallel converter comprises a complimentary transistor pair and three current mirrors. The transistor pair and a first current mirror and a second current mirror act as a rectifier. The complimentary transistor pair has I.sub.in connected to common sources, and common gates connected to ground. A first current mirror has its input connected to the drain of the n-type transistor of the complimentary pair and its output connected to the drain of the p-type transistor. The second current mirror acts as an amplifier by having its input transistors being half the width of the corresponding output transistors. The second mirror has its input connected to the output of the first current mirror, and its output going to I.sub.out. The third current mirror acts to subtract I.sub.