Patents Examined by T. N. Quach
  • Patent number: 7768013
    Abstract: A vertical structure thin film transistor is provided. The vertical structure thin film transistor has a stacked structure of a substrate, a first electrode, a dielectric thin film, a second electrode, a semiconductor thin film, and a third electrode, wherein current flows between the second and third electrodes perpendicularly to the substrate and is modulated by an electric field generated from the first electrode parallel to the current.
    Type: Grant
    Filed: November 25, 2003
    Date of Patent: August 3, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Seong Hyun Kim, Taehyoung Zyung
  • Patent number: 7408193
    Abstract: A semiconductor device packaged in three dimensions comprises a first thin film device, a second thin film device, and a third thin film device, each of the first, second, and third thin film devices comprising a first insulating film, a first electrode formed over the first insulating film, a second insulating film formed over the first electrode, first and second thin film transistors formed over the second insulating film, wherein the first thin film transistor is connected to the first electrode through a first contact hole, a third insulating film formed over the first and second thin film transistor, a second electrode formed over the third insulating film, wherein the second electrode is connected to the second thin film transistor through a second contact hole, and a fourth insulating film formed over the third insulating film and the second electrode.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: August 5, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akira Ishikawa
  • Patent number: 7391075
    Abstract: A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high ? material.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: June 24, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-hun Jeon, Jeong-hee Han, Chung-woo Kim
  • Patent number: 7388276
    Abstract: A varactor is configured with first and second conducting layers, spaced apart from one another such that a given voltage can be applied across the first and second conducting layers. Further, an insulator arrangement includes at least one insulator layer disposed between the first and second conducting layers, configured to cooperate with the first and second conducting layers to produce a charge pool which changes responsive to changes in the given voltage such that a device capacitance value between the first and second conducting layers changes responsive to the given voltage. The insulator arrangement can include one layer, two distinct layers or more than two distinct layers. One or more of the layers can be an amorphous material. A zero-bias voltage version of the varactor is also described.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: June 17, 2008
    Assignee: The Regents of the University of Colorado
    Inventor: Michael J. Estes
  • Patent number: 7372103
    Abstract: A MOS field plate trench transistor device is disclosed. In one embodiment, in order to obtain a lowest possible on resistance, in the case of a MOS field plate trench transistor device having a body contact hole, it is proposed to form the avalanche breakdown region preferably in an end region of a provided trench structure by virtue of the fact that a mesa region with the body contact region in the semiconductor region as intermediate region in a direction running perpendicular to the first direction and with respect to an adjacent MOS transistor device has a width DMesa, the value of which corresponds to the value of the width DTrench of the trench structure in this direction or exceeds said value and does not go beyond 1.5 times said value, so that the following holds true: DTrench?DMesa?1.5·DTrench. As an alternative, the width DMesa is chosen such that the body contact hole precisely still has space, but the breakdown region is in any event shifted into the end region.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: May 13, 2008
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Zundel, Franz Hirler
  • Patent number: 7372089
    Abstract: A solid-state image sensing device provided with photoelectric conversion films stacked above a semiconductor substrate, comprising: first impurity regions as defined herein; second impurity regions as defined herein; signal charge reading regions as defined herein; and third impurity regions as defined herein.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: May 13, 2008
    Assignee: FUJIFILM Corporation
    Inventors: Tomoki Inoue, Shinji Uya
  • Patent number: 7371599
    Abstract: An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate electrode. A spacer surrounds the gate electrode on the dielectric layer.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: May 13, 2008
    Assignee: United Microeletronics Corp.
    Inventor: Jhy-Jyi Sze
  • Patent number: 7372101
    Abstract: A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the back side of the device. In another embodiment, the trench-fill material is separated from the device by an insulating layer, and serves as a back gate structure.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: May 13, 2008
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Patent number: 7368347
    Abstract: Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.
    Type: Grant
    Filed: October 3, 2006
    Date of Patent: May 6, 2008
    Assignee: Spansion LLC
    Inventors: Amol Ramesh Joshi, Ning Cheng, Minghao Shen
  • Patent number: 7368758
    Abstract: A method is provided for producing a housing body for optoelectronic components that are reliable and inexpensive. The method creates a hermetic joint between a metal sleeve and a glass pane by joining together a housing element and a preferably metallic housing arrangement. The housing element and the housing arrangement are brought into contact with a glass solder, before the housing element and housing arrangement are joined. The glass solder is applied as a shapeable material, in particular as a paste. The glass solder is pre-vitrified and has its shape fixed by energy being introduced at least once, in particular as a result of organic constituents being burnt off. After the housing element has been inserted into the housing arrangement, a joint that is hermetic at least in regions, is produced between the glass pane and housing arrangement.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: May 6, 2008
    Assignee: Schott AG
    Inventors: Dietrich Mund, Bernd Hammer, Robert Hettler, Klaus Schachtelbauer, Edeltraud Sausenthaler, Markus Maier
  • Patent number: 7368774
    Abstract: A capacitor includes a lower electrode, a first dielectric film composed of lead zirconate titanate niobate formed above the lower electrode, a second dielectric film composed of lead zirconate titanate or lead zirconate titanate niobate with a Nb composition smaller than a Nb composition of the lead zirconate titanate niobate composing the first dielectric film, and an upper electrode formed above the second dielectric film.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: May 6, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Yasuaki Hamada, Takeshi Kijima
  • Patent number: 7365418
    Abstract: A multi-chip structure at least including a first chip, a second chip and a first thermal-conductive layer is provided. The first chip has a first surface and a plurality of first pads disposed on the first surface. The second chip has a second surface facing the first surface and a plurality of second pads disposed on the second surface. The first thermal-conductive layer is disposed between the first chip and the second chip and includes a thermal-conductive area, a plurality of first electrical connection members and a plurality of first dielectric areas. The first electrical connection members disposed in the first thermal-conductive layer are used to electrically connect the first surface and the second surface. The first dielectric areas surround and insulate the first electrical connection members from the thermal-conductive area.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: April 29, 2008
    Assignee: VIA Technologies, Inc.
    Inventor: Chi-Hsing Hsu
  • Patent number: 7361988
    Abstract: Various methods and apparatuses are described in which a printed circuit board has trace lines. Input/output pads on the printed circuit board may have approximately the same width dimension as a trace line connected to those input/output pads. A first group of vias in the printed circuit board may be aligned into a planar line with a set corridor spacing between adjacent of groups of vias also aligned into a planar line with the same axis to allow a routing space for lines in multiple layers of the printed circuit board to occur in the routing space established by the set corridor spacing.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventors: Thomas O. Morgan, James D. Jackson, Weston C. Roth
  • Patent number: 7361954
    Abstract: Disclosed is a power semiconductor device, including: a gate electrode having a cross section having a length in a vertical direction, and having a shape extending in a direction orthogonal to the cross section; a gate insulating film surrounding the gate electrode; an n-type source layer positioning to face the gate electrode via the gate insulating film; a p-type base layer adjacent to the n-type source layer and positioning to face the gate electrode via the gate insulating film; an n-type base layer adjacent to the p-type base layer and positioning to face the gate electrode via the gate insulating film without being in contact with the n-type source layer; and a main electrode being in contact with the n-type source layer and the p-type base layer with plural lateral planes extending in a direction crossing the direction in which the gate electrode is extending.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: April 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Sugiyama, Masakazu Yamaguchi
  • Patent number: 7358530
    Abstract: An improved transistor array for a display or sensor device is described. The display or sensor device includes a plurality of pixels. Each pixel includes a width and a length. Each pixel is addressed by a transistor. The transistor addressing each pixel has a channel with a channel width. Each channel width is greater than the width or length of the pixel being addressed. By fabricating transistors with extremely long channel widths, lower mobility semiconductor materials can easily be used to fabricate the display device.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: April 15, 2008
    Assignee: Palo Alto Research Center Incorporated
    Inventors: William S. Wong, Jeng Ping Lu, Alberto Salleo, Michael L. Chabinyc, Raj B. Apte, Robert A. Street
  • Patent number: 7358560
    Abstract: A non-volatile memory device includes a semiconductor substrate having an active region defined by isolation films that extend along a first direction. A control gate line extends along in a second direction perpendicular to the first direction. First and second floating gates are formed on the active region and below the control gate line. An island conductive line is formed between the first and second floating gates and within the isolation films. The island conductive line extends along the first direction and is configured to receive a voltage in order to prevent interference between the first and second floating gates.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: April 15, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Keun Woo Lee
  • Patent number: 7358558
    Abstract: A floating gate of a flash memory device is formed in a moat formed in an isolation film. Therefore, an electric field applied between a control gate and a channel region upon cycling can be precluded or mitigated. A distance between the control gate and the channel region is set greater than a predetermined value. Therefore, an electric field applied between the control gate and the channel region upon cycling can be mitigated. As a result, a data retention characteristic and an endurance characteristic can be improved.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: April 15, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Keun Woo Lee
  • Patent number: 7358565
    Abstract: An n-type first base layer is formed on a semiconductor substrate 1 having a first major surface and a second major surface, and a p-type second base layer is formed thereon. Between the first base layer and the second base layer, a carrier stored layer is formed. The carrier stored layer has a high-concentration impurity layer and a low concentration impurity layer, and the high-concentration impurity layer has a thickness of 1.5 ?m or more and an impurity concentration therethrough is made to be 1.0√ó1016 cm?3 or more throughout the layer.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: April 15, 2008
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tatsuo Harada
  • Patent number: 7355277
    Abstract: A die package and a method and apparatus for integrating an electro-osmotic pump and a microchannel cooling assembly into a die package.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: April 8, 2008
    Assignee: Intel Corporation
    Inventors: Alan M. Myers, R. Scott List, Gilroy J. Vandentop
  • Patent number: 7355276
    Abstract: A circuit assembly for mounting one or more integrated circuits that effectively dissipates heat generated by the integrated circuits, and a corresponding method for fabricating such a circuit assembly. The circuit assembly comprises a substrate, a thermally-conductive adhesive layer and a heat-dissipating layer. The substrate includes an opening extending between a first surface and a second surface of the substrate. An integrated circuit is to be mounted on the first surface of the substrate substantially coincident with the opening. The thermally-conductive adhesive layer is at least partially disposed within the opening in the substrate. The heat-dissipating layer is disposed on the second surface of the substrate and includes a raised portion that at least partially extends through the opening in the substrate.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: April 8, 2008
    Assignee: Maxtor Corporation
    Inventors: Mark R. Lanciault, Mark R. Dunbar, Stanislaw Dobosz