Patents Examined by T. T. Lam
  • Patent number: 5774007
    Abstract: A clock distributing apparatus which can decrease the clock skew and can prevent the swing of a signal on clock transmission lines and can achieve a low power consumption, a lower noise of a power supply, and a high speed operation, wherein converts clock signals adjusted in phase to the same phase as a reference clock by a PLL circuit to current signals by voltage/current converters and sends the current signals to clock transmission lines and converts the current signals transmitted to the clock transmission lines to voltage signals by current/voltage converters and sends the voltage signals to circuit blocks of an integrated circuit.
    Type: Grant
    Filed: October 16, 1996
    Date of Patent: June 30, 1998
    Assignee: Sony Corporation
    Inventor: Mitsuo Soneda
  • Patent number: 5774003
    Abstract: A flip-flop cell having a main data input, a main scan data input, a main data output and a main clock input. The flip-flop cell includes a multiplexer having first and second inputs and an output. The first input is coupled to the main data input of the flip-flop cell and the second input is coupled to the main scan data input of the flip-flop cell. A first latch has a data input, a data output and an inverting clock input. The data input of the first latch is coupled to the output of the multiplexer. A second latch has a data input, a data output and a non-inverting clock input. The data input of the second latch is coupled to the data output of the first latch. A third latch has a data input, a data output and an inverting clock input. The data input of the third latch is coupled to the data output of the second latch, and the data output of the third latch is coupled to the main data output of the flip-flop cell.
    Type: Grant
    Filed: October 9, 1996
    Date of Patent: June 30, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Fazal Ur Rahman Qureshi, Martin William Person
  • Patent number: 5770962
    Abstract: A circuit that includes a series arrangement of a capacitive element (C) and an active component (M10) forming an equivalent resistor. A DC current source (120 is connected to the active component, and a transistor (M11, 11) is provided for altering the conductance of the active component and fixing the mean level of a AC voltage (U.sub.ac). Such a voltage is applied to the terminals of the series arrangement, and the biased voltage having the desired mean level (U.sub.out) is tapped off the node (10) between the capacitive element (C) and the active component. A capacitive voltage divider (13) is also provided for modulating the DC current (i) passing through the active component (M10), with a fraction of the AC voltage to be biased. The circuit is particularly applicable to the determination of the mean level of the voltage produced by a quartz oscillator.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: June 23, 1998
    Assignee: Centre Suisse D'Electronique et de Microtechnique SA
    Inventor: Daniel Aebischer
  • Patent number: 5770952
    Abstract: A timer which provides both the surveying and counting functions. It contains a counter, a multiplexer, an edge-triggered controller, a time-base latching circuit, and a pulse-detecting circuit. It not only can be used as a timer, but can also be used as a counter to count the number of the external signals so as to detect the width of an external signal.
    Type: Grant
    Filed: June 13, 1995
    Date of Patent: June 23, 1998
    Assignee: Holtek Microelectronics Inc.
    Inventor: Kuo-Cheng Yu
  • Patent number: 5767717
    Abstract: A high performance dynamic logic compatible transparent latch is provided. The latch comprises a first switchable invertor circuit, a second invertor circuit, and a third switchable invertor circuit. The first invertor, having a data input, a clock input and an output, is enabled by a first phase of an input clock and is disabled by a second phase of the input clock. The second invertor has an input connected to the first invertor output. The third invertor has a clock input, and is enabled by the second phase of the input clock and disabled by the first phase of the input clock, and further has an input connected to the second invertor output and an output connected to the second invertor input.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: June 16, 1998
    Assignee: International Business Machines Corporation
    Inventors: Eric Bernard Schorn, Raymond George Stephany
  • Patent number: 5767714
    Abstract: A PLL circuit which is used as a reproducing clock forming circuit of a digital signal reproducing apparatus. The PLL circuit is strong against noises and has stable characteristics. Comparison outputs of a phase comparator 3 are outputted in a form of balance (differential) signals and are supplied to a loop filer 4. Output signals of the loop filter 4 are supplied to control voltage input terminals of a VCO 5 in a form of the balance signals. In-phase components of the noises included in control voltages can be cancelled. Time constants of the loop filter can be switched by bipolar transistors Tr31 and Tr32. A balance of the balance signals is not broken by base currents of the transistors Tr31 and Tr32.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: June 16, 1998
    Assignee: Sony Corporation
    Inventors: Yasutaka Kotani, Yasuo Sakura, Shiro Miyagi
  • Patent number: 5767721
    Abstract: A switch circuit is disclosed including a first FET device coupled in series with an input terminal and an output terminal. A second FET device coupled to the first device in a shunt configuration. The FET devices operative in a first mode to enable electronic signal transmission between the input and output terminals, and further operative in a second mode to prevent the electronic signal transmission. A biasing network for enabling a single control signal to operate the FET devices in both the first and second modes.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: June 16, 1998
    Assignee: ITT Industries, Inc.
    Inventor: Raymond J. Crampton
  • Patent number: 5764090
    Abstract: A write-control circuit including a pulse processor and a waveform shifter is disclosed. The pulse processor is provided for processing a first waveform. When the first waveform has a bandwidth wider than a first delay, the waveform goes through the pulse processor without change. Otherwise, a second delay is added to trailing edge of the first waveform. The waveform shifter is provided for shifting the output waveform of the pulse processor as a second waveform. The pulse processor consists of a pulse generator, a trailing edge delay circuit, a NOR gate and an inverter. The pulse generator, which generates a finite-length pulse by the first waveform, includes a delay chain and a NAND gate. The delay chain may consist of an odd number of delay units. The trailing edge delay circuit includes an even number of delay units and a NAND gate for adding the second time delay to the trailing edge of the finite-length pulses.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: June 9, 1998
    Assignee: United Microelectronics Corporation
    Inventors: Wen-Chih Yeh, Hsiao-Yueh Chang
  • Patent number: 5760617
    Abstract: A voltage-to-frequency converter having an analog-to-digital converter, based on analog components, for converting samples of an analog signal into corresponding digital words and a digital-to-frequency converter, based on digital components, for converting the digital words into a train of pulses having a pulse repetition frequency related to the analog signal. With such an arrangement, the digital-to-frequency converter and the analog-to-digital converter are adapted to operate at different rates. Therefore, the analog-to-digital converter may be optimized at one operating rate while the digital-to-frequency converter is adapted to operate at a higher operating rate and over a wide range of operating rates. This arrangement thereby enables a slower, analog component based, analog-to-digital converter to be used fabricated with CMOS technology along with the higher, variable operating rate, digital component based, digital-to-frequency converter.
    Type: Grant
    Filed: August 20, 1996
    Date of Patent: June 2, 1998
    Assignee: Analog Devices, Incorporated
    Inventors: Michael C. Coln, Eric Nestler
  • Patent number: 5757213
    Abstract: In a preferred embodiment, a multi-configurable output driver, including: circuit apparatus to provide driving current to an inductive load; and the circuit apparatus being configurable, without the addition or rearrangement of components, in at least two different output topographies.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: May 26, 1998
    Assignee: Delco Electronics Corp.
    Inventor: David Dale Moller
  • Patent number: 5757221
    Abstract: An analog arithmetic circuit directly divides an input voltage by another input voltage with high accuracy without requiring a logarithmic conversion process or an adjustment process. The analog arithmetic circuit includes: an integrator for integrating a dividend signal and a feedback signal; a hysteresis comparator having two threshold levels to compare an output signal of the integrator and generates a comparison output; a limiter which receives the comparison output and a divisor signal and generates the feedback signal that is proportional to the divisor signal; an average circuit connected to an output of the hysteresis comparator to generates an average value of the comparison output as a quotient signal.
    Type: Grant
    Filed: May 23, 1996
    Date of Patent: May 26, 1998
    Assignee: Advantest Corp.
    Inventor: Mishio Hayashi
  • Patent number: 5757216
    Abstract: In a phase synchronous circuit, a phase of a reference signal and a phase of a compared signal that corresponds to an oscillation signal output by an oscillator are compared with each other a phase comparison output signal which corresponds to a phase difference is fed to the oscillator via a filter so that the oscillator is controlled. A control circuit provided in the phase synchronous circuit causes an output value of the phase comparison output signal to vary nonlinearly in accordance with the phase difference.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: May 26, 1998
    Assignee: Fujitsu Limited
    Inventor: Toshihiko Murata
  • Patent number: 5757211
    Abstract: An integrated circuit motor controller having two or more integrated resistor dividers which produce signals to be compared with each other is disclosed. The circuit is designed to substantially reduce the dependency of the comparison on the reverse bias of the junctions between diffused resistors in the integrated resistor dividers and the silicon into which they are diffused.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: May 26, 1998
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: William Aidan Phillips
  • Patent number: 5757212
    Abstract: A pin-configurable frequency synthesizer for providing a choice of physical pin assignments/configurations without costly design and/or bonding changes. A functional block, having a plurality of functional conductors, is provided. The pin-configurable frequency synthesizer is housed in a chip package that includes a plurality of physical pins. A configuration matrix having a plurality of transmission circuits for connecting the functional conductors to the physical pins is also provided. A control circuit for controlling the transmission circuits of the configuration matrix is further provided. This control circuit includes programming logic and a logic array for generating control signals for each of the transmission circuits of the configuration matrix. These control signals direct the transmission circuits to selectively couple each functional conductor to a respective physical pin in accordance with a desired pin assignment.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: May 26, 1998
    Assignee: Cypress Semiconductor Corp.
    Inventor: Piyush B. Sevalia
  • Patent number: 5754073
    Abstract: A multiplier containing first and second squaring circuits, in which the first squaring circuit has first and second differential transistor-pairs and the second squaring circuit has third and fourth ones. A positive output end of the first squaring circuit and an opposite output end of the second squaring circuit are coupled together, and an opposite output end of the first squaring circuit and a positive output end of the second squaring circuit are coupled together, which constitutes a pair of differential output ends of the multiplier. Sum and difference of first and second input voltages are applied to the differential input ends of the first and second squaring circuits, respectively. A first DC voltage is commonly applied across respective input ends of the first and second transistor-pairs, and a second one across the other input ends thereof. The second DC voltage is applied equal in polarity to the first DC voltage.
    Type: Grant
    Filed: November 17, 1993
    Date of Patent: May 19, 1998
    Assignee: NEC Corporation
    Inventor: Katsuji Kimura
  • Patent number: 5751175
    Abstract: In a clock signal control circuit of a semiconductor device, a first clock signal is externally supplied to a first terminal of the semiconductor device in an external clock signal mode. In an external element using mode, a second clock signal is generated on said first terminal by a clocked inverter and a self-biasing resistor composed of a P-channel MOS transistor and N-channel MOS transistor, using elements externally connected between the first terminal and a second terminal of the semiconductor device. The clock signal on said second terminal in the external clock signal mode or the external element using mode is supplied to the internal circuit of the semiconductor device using a Schnmitt trigger type of logic gate. In the external clock signal mode, the clocked inverter and the self-biasing resistor are turned off such that the generation of the second clock signal is inhibited. Further, in a clock signal stop mode, the supply of the clock signal is inhibited.
    Type: Grant
    Filed: January 30, 1996
    Date of Patent: May 12, 1998
    Assignee: NEC Corporation
    Inventor: Hirohisa Imamura
  • Patent number: 5751180
    Abstract: Power consumption, electromigration, joule heating, and voltage supply ringing are reduced in digital integrated circuits by reducing crowbar current. In one embodiment, crowbar current in a buffer circuit (71) is reduced by electrically connecting the drain region of a PMOS transistor (73), in a first inverter, to a gate electrode (84) of an NMOS transistor (79) and a gate electrode (82) of a PMOS transistor (77), in a second inverter, through a first conductive interconnect (78). In addition, the drain region of the NMOS transistor (75) in the first inverter is electrically connected to the gate electrode (84) of the NMOS transistor (79) and to the gate electrode (82) of the PMOS transistor (77), in the second inverter, through a second conductive interconnect (80). These conductive interconnects allow crowbar current, which is created during a transition between logic states, to be reduced.
    Type: Grant
    Filed: September 3, 1996
    Date of Patent: May 12, 1998
    Assignee: Motorola, Inc.
    Inventor: Michael Lee D'Addeo
  • Patent number: 5748031
    Abstract: A programmable hybrid fuse circuit having a laser fuse and an electrical fuse. The programmable hybrid fuse circuit includes a reference circuit, a current mirror and at programming circuit. The reference circuit generates a reference current mirror. The current mirror generates an output current in response to the reference current. The current mirror has at least one current output which is coupled to a programming circuit to receive the output current. The programming circuit includes a laser fuse and an electrical fuse coupled in a serial order such that either the laser fuse or the electrical fuse is capable of being blown during programming. The programming circuit generates an output signal having a first voltage level or a second voltage level dependent on whether one of the fuses is blown during programming.
    Type: Grant
    Filed: February 1, 1996
    Date of Patent: May 5, 1998
    Assignee: Cypress Semiconductor, Corporation
    Inventor: Scott C. Best
  • Patent number: 5748016
    Abstract: A driver circuit comprising (i) a pair of complementary MOS (CMOS) transistors connected in series and receiving an identical input signal, and (ii) a pair of control transistors changing a threshold voltage state of each of the pair of CMOS transistors by applying a plurality of voltages to a body terminal of each of the pair of CMOS transistors depending upon the ON/OFF state of each of the pair of CMOS transistors. Such a driver circuit is capable of reconciling a high-speed operation with a low power consumption under low power supply voltage conditions.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: May 5, 1998
    Assignee: NEC Corporation
    Inventor: Susumu Kurosawa
  • Patent number: 5748017
    Abstract: An improved system and method of determining the linearity of a ramp signal, including a ramp generator (11) for generating a ramp signal and a vernier delay (15) to provide scan stop signals where the samples are peak detected (17) and stored (21). The ramp generator (11) outputs are divided into equal sections controlled by a precise crystal controlled oscillator (25). The stored signals are processed and compared to detect errors.
    Type: Grant
    Filed: July 19, 1996
    Date of Patent: May 5, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Michael C. Storey, Lawane Luckett