Abstract: Requests are identified as being for a cacheable object or a non-cacheable object according to information included in a Uniform Resource Locator (URL) associated with the object. For example, the URL may include a port designation for requests for cacheable objects (e.g., images and the like). Thus, a request may be recognized as being for a cacheable or non-cacheable object according to the port on which the request is made. In some cases, requests for non-cacheable objects may be made on port 80. A router may be thus configured to recognize a request as being for a cacheable object or a non-cacheable object according to a port on which the request is received and redirect it to a cache as appropriate.

Abstract: Conventional information storage systems are subject to numerous practical constraints such as contiguity in the physical locations of blocks and the requirement that storage blocks be created in advance. Information retrieval in these systems has required the creation of indices, which take a long time to generate, and the structure of these systems makes them prone to deadlock since the indices are updated and the range of exclusion broadened when the referent information is modified. This invention utilizes the random access facilities of semiconductors to achieve high speeds and minimize the maintenance load. This invention introduces location tables and alternate-key tables to replace these indices. It also stores multiple records in a single block and can handle variable-length records and spanned records. The location tables manage the storage blocks.

Abstract: A method of storing values that involves splitting each value into a n-bit value and an overflow value, and storing, in a main table, the n-bit values in order of increasing magnitude of the values. For each overflow value, the position of the smallest n-bit value is stored in an overflow table. To retrieve a value, the position of the corresponding n-bit value is compared to the positions stored in the overflow value to determine the overflow value of the n-bit value. The actual value is then obtained from the n-bit value and its overflow value.

Abstract: A cache is coupled to receive an access which includes a cache allocate indication. If the access is a miss in the cache, the cache either allocates a cache block storage location to store the cache block addressed by the access or does not allocate a cache block storage location in response to the cache allocate indication. In one implementation, the cache is coupled to an interconnect with one or more agents. In such an implementation, the cache accesses may be performed in response to transactions on the interconnect, and the transactions include the cache allocate indication. Thus, the source of a cache access specifies whether or not to allocate a cache block storage location in response to a miss by the cache access. The source may use a variety of mechanisms for generating the cache allocate indication.

Abstract: The present invention comprises a method, apparatus, and machine-readable medium to pre-allocate a space for data. Embodiments of the present invention are designed to pre-allocate a space for data in nonvolatile memory. More specifically, embodiments may provide a reservation for a data write, so sufficient unallocated space can be confirmed as available for the write prior to actually writing the data to the nonvolatile memory.

Abstract: A processor of a system initiates memory read transactions on a bus and provides information regarding the speculative nature of the transaction. A bus device, such as a memory controller, then receives and processes the transaction, placing the request in a queue to be serviced in an order dependent upon the relative speculative nature of the request. In addition, the processor, upon receipt of an appropriate signal, cancels a speculative read that is no longer needed or upgrades a speculative read that has become non-speculative.

Abstract: A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been performed and are then sent to a host system. States of ranges of disk addresses (activity bins) are stored in nonvolatile storage elements associated with the ranges. The states allow rebuild times to be reduced after power failures and drive failures. A range is in a Changing state if at least one of the addresses is the target of a write operation that has been initiated but not completed. The range is in a Stable state if no addresses are the target of an uncompleted write operation. Two additional states are used to identify ranges of disk addresses that have been zeroed or never been written to. The additional states allow substantial reductions in RAID volume creation times.

Abstract: Column addresses are generated by a burst controller that includes respective latches for the three low-order bits of a column address. The two higher order bits of the latched address bits and their complements are applied to respective first multiplexers along with respective bits from a burst counter. The first multiplexers apply the latched address bits and their complements to respective second multiplexers during a first bit of a burst access, and bits from a burst counter during the remaining bits of the burst. The second multiplexers are operable responsive to a control signal to couple either the latched address bits or their complements to respective outputs for use as an internal address. The control signal is generated by an adder logic circuit that receives the two low-order bits of the column address.

Abstract: A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been performed and are then sent to a host system. States of ranges of disk addresses (activity bins) are stored in nonvolatile storage elements associated with the ranges. The states allow rebuild times to be reduced after power failures and drive failures. A range is in a Changing state if at least one of the addresses is the target of a write operation that has been initiated but not completed. The range is in a Stable state if no addresses are the target of an uncompleted write operation. Two additional states are used to identify ranges of disk addresses that have been zeroed or never been written to. The additional states allow substantial reductions in RAID volume creation times.

Abstract: A synchronous memory device that avoids erroneous output while internal initialization is taking place. In one embodiment, a tri-state logic circuit is used to selectively tri-state an output buffer during memory initialization. The output buffer is used to output data from a memory array to DQ lines. Tri-stating the output buffer floats the DQ lines. Thus, data in the DQ lines is not output in response to commands. Control circuitry signals the tri-state logic circuit to tri-state the output buffer during initialization. In another embodiment, an external processor can be used to provide a read status command to the memory to determine the status of memory initialization. In this embodiment, tri-stating the output buffer during initialization is momentarily overridden to respond to the read status command.

Abstract: A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is “0”, a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers.

Abstract: A buffering system attached to a memory for holding write-once, read-once data that is accessed by one or more peripheral devices. Data that is otherwise destined to be written to main memory is written, instead, into a storage buffer. The buffer is written using an address contained in a write pointer that is updated according to a predetermined pattern after the write operation. After updating the write pointer, if the address equals the read pointer, some or all of the buffer is flushed to the memory. Data is read from the buffer using an address contained in a read pointer that is updated according to the same predetermined pattern after the read operation. Any deviation from the pattern in either writing or reading the buffer causes the some or all of the buffer to be flushed to main memory and the read pointer to be updated accordingly.

Abstract: A data processing system and method involving a data requesting element and a first memory element from which said data requesting element requests data is described. An example of such a system is a processor and a first level cache memory, or two memories arranged in a hierarchy. A second memory element is provided between the first memory element and the requesting element. The second memory element stores data units read out of said first memory element, and performs a prefetch procedure, where said prefetch procedure contains both a sequential sub-procedure and a sub-procedure based on prefetch data identifiers associated with some of the data units.

Abstract: N_Port_Name information capable of distinctly identifying a host computer has seen set in a microprocessor 42 of a storage controller 40 prior to start-up of host computers 10, 20, 30; upon startup of the host computers 10, 20, 30, when the storage controller 40 receives a frame issued, then the microprocessor 42 operates to perform comparison for determining whether the N_Port_Name information stored in the frame has been already set in the microprocessor 42 and registered to the N_Port_Name list within a control table maintained. When such comparison results in match, then continue execution of processing based on the frame instruction; if comparison results in failure of match, then reject any request.

Abstract: The invention provides a method and system for performing additional processing on CAM hit results, in which the additional processing does not add to the complexity or size of the CAM chip, can be altered after manufacture of the CAM chip, and does not delay other operations of the CAM. The CAM hit results are presented as indices from the CAM and sent to a hit result register file where they are stored. The contents of the hit result register file can be processed by other hardware or software coupled to the CAM. The index associated with the CAM input tag can be accessed using the hit result register file and a register indirect operation. The index associated with the CAM input tag can be used for CAM management functions in conjunction with (such as in parallel or pipelined) other CAM functions.

Abstract: A method for selecting an order of data transmittal based on system bus utilization of a data processing system. The method comprises the steps of coupling system components to a processor within the data processing system to effectuate data transfer, dynamically determining based on current system bus loading, an order in which to retrieve and transmit data from the system component to the processor, and informing the processor of the order selected by issuing to the data bus a plurality of selected order bits concurrent with the transmittal of the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is a cache and a system monitor monitors the system bus usage/loading.

Abstract: A data carrying device having a memory space for storing data at a plurality of locations. The memory space includes a static area residing at a fixed location; an index area residing at a first dynamically allocatable location; and an application area residing at a second dynamically allocatable location. The static area is configured to hold data pointing to the location of the index area and the index area is configured to hold data indicative of applications or programs residing within the application area.

Abstract: A file access processor, which accesses a storage unit storing a plurality of files therein based on an access request from a request source, according to the present invention has a mirroring relation storage unit in which mirroring relation information is stored, wherein the mirroring relation information includes a mirroring attribute value indicating whether or not each file is to be mirror-accessed and, when the file is to be mirror-accessed, mirroring file information indicating a mirroring file corresponding to the file; and a file access processing unit which references the mirroring relation information based on the access request and accesses the storage unit.

Abstract: A most recently used bit (25) is used to determine if a data transfer should occur from a fill buffer (20) into a data memory (32) in a cache (15). If the data to be displaced in the data memory (32) has been referenced more recently than the data present in the fill buffer (20), then the transfer should not occur. When a cache miss does occur, a control register (50) is used to determine the conditions for loading the fill buffer (20).

Abstract: A method of communicating information between a host device and a potentially portable module device which measures thermal accumulation over time via a temperature controlled counter. The temperature controlled counter may operate using substantially Arrhenius' law. The host device communicates with the portable module via a single wire bidirectional data bus. The single wire bus and one-wire communication protocol allows data flow between a host and a plurality of devices connected to the single wire bus. The single wire bus allows for a great versatility of uses for the portable module.