Abstract: The present disclosure discloses a parameter configuration method and apparatus, and a display device, belonging to the field of display technologies. The method is applicable to a controller connected to a plurality of drivers, and includes: sending a component information request instruction to a first driver over a first signal line, wherein the first driver is one of the plurality of drivers; receiving a component information response instruction sent over the first signal line by the first driver, wherein the component information response instruction includes component information; determining configuration parameters corresponding to the component information; and performing parameter configuration for the plurality of drivers by using the determined configuration parameters.

Abstract: The embodiments of the present disclosure disclose a firmware boot implementation method based on Flash chip simulation, the method comprising: when there are at least two MCUs, one of the MCUs is selected as a master MCU and each remaining MCU is as slave MCU which is connected with the master MCU respectively, and the master MCU is connected with a Flash chip; when the master MCU is started, the master MCU is started by reading firmware data in the Flash chip; when the slave MCU is started, the master MCU controls the slave MCU to be powered on, and the slave MCU sends a request for reading the firmware data to the master MCU; the master MCU transmits the request to the Flash chip, and transmits the firmware data returned by the Flash chip to the slave MCU, so as to start the slave MCU.

Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.

Abstract: The invention introduces a method for programming data of page groups into flash units to include steps for: obtaining, by a host interface (I/F) controller, user data of a page group from a host side, wherein the page group comprises multiple pages; storing, by the host I/F controller, the user data on the pages in a random access memory (RAM) through a bus architecture, outputting the user data on the pages to an engine via an I/F, and enabling the engine to calculate a parity of the page group according to the user data on the pages; obtaining, by a direct memory access (DMA) controller, the parity of the page group from the engine and storing the parity of the page group in the RAM through the bus architecture; and obtaining, by a flash I/F controller, the user data on the pages and the parity of the page group from the RAM through the bus architecture, and programming the user data on the pages and the parity of the page group into a flash module.

Abstract: A computer-implemented method at a data management system comprises: retrieving start and end times of a backup of a database; retrieving time stamps of log backups of the database; retrieving sequence numbers of the log backups; generating a graphical user interface illustrating a timeline of availability of database restoration and unavailability; making a second backup of the database; illustrating, on the graphical user interface during the making, pending availability of the second database backup; receiving a command to restore the database at an available time as illustrated by the graphical user interface; and restoring the database.

Abstract: Devices, methods, and media are described for unmap support in coarse mapped storage. In one embodiment a controller of a memory sub-system manages a set of metadata for super management units (SMU) of the memory sub-system, wherein each SMU of the memory sub-system comprises a plurality of data management units (MU), and wherein each MU comprises a plurality of addressable memory elements as part of a coarse memory storage of the memory sub-system. The controller processes a trim command for a first SMU of the plurality of SMUs, and adjusts a trim bit associated with metadata for the first SMU. This trim bit can then be used to manage read and write operations as the trimmed unit waits to be written with an unmap data pattern. Similarly, a trim bit in MU metadata can be used manage related operations to prevent memory access errors.

Abstract: A controller may control a memory device including memory blocks. The controller may include a processor configured to generate a command queue in response to a write command, a wear level management block configured to check a wear level of each memory block based on an erase/program pulse count variation, and manage the memory blocks such that each memory block belong to an SLC memory block group or an MLC memory block group, and a memory device control circuit configured to control the memory device to perform a write operation in response to the command queue. The memory device control circuit may select a first memory block belong to the SLC memory block group when the write operation is an operation for important data, and select a second memory block belong to the MLC memory block group when the write operation is an operation for normal data.

Abstract: Disclosed herein are systems, methods, and apparatuses where a controller can automatically manage a physical infrastructure of a computer system based on a plurality of system rules, a system state for the computer system, and a plurality of templates. Techniques for automatically adding resources such as computer, storage, and/or networking resources to the computer system are described. Also described are techniques for automatically deploying applications and services on such resources. These techniques provide a scalable computer system that can serve as a turnkey scalable private cloud.

Abstract: In general, in one aspect, the invention relates to a method for processing data, the method includes obtaining, by a host operating system (OS) on a host computing device, a notification of a power down. The further includes, in response to the notification, performing a data storage analysis on data stored in host OS memory to identify a plurality of processing tasks to perform on the data, making a first determination, based on the data storage analysis, that data processing is to be offloaded to a graphics processing unit, and in response to the first determination: sending a data processing request to the processing unit, obtaining a second notification associated with processed data from the graphics processing unit, and storing the processed data in a backup storage device.

Abstract: A method and apparatus managing online transaction using a computer system are disclosed. According to the present invention, a target request is received by a CPU coupled to a main memory and a memory application co-processor via a memory bus. The CPU then stores the target request onto the memory application co-processor coupled to a storage class memory. The memory application co-processor then locates target contents, inside the storage class memory, where the target key-word is specified in the target request. The CPU or a coupled device then accesses the target contents associated with the target key-word inside the storage class memory directly without copying the target contents associated with the target key-word inside the storage class memory to or from the main memory.

Abstract: A system and method for providing dynamic I/O virtualization is herein disclosed. According to one embodiment, a device capable of performing hypervisor-agnostic and device-agnostic I/O virtualization includes a host computer interface, memory, I/O devices (GPU, disk, NIC), and efficient communication mechanisms for virtual machines to communicate their intention to perform I/O operations on the device. According to one embodiment, the communication mechanism may use shared memory. According to some embodiments, the device may be implemented purely in hardware, in software, or using a combination of hardware and software. According to some embodiments, the device may share its memory with guest processes to perform optimizations including but not limited to a shared page cache and a shared heap.

Abstract: According to one embodiment, a memory system is capable of being connected to a host. The memory system includes a nonvolatile memory and a controller that receives information regarding an operating state of the host. The controller controls the nonvolatile memory according to commands from the host and selects a parameter for interrupt coalescing for transmissions to the host of interrupts related to command completion notices for the commands from the host based on the information regarding the operating state of the host.

Abstract: In some implementations, a computing device may configure a new device based on a current state of an old device, including settings, preferences, and other user data. The data may be transferred from the old device to the new device, and then relocated according to a manifest that details positions of the data on the old device. The destination device may be rebooted into a configuration mode to allow for the relocation of the transferred data, and then rebooted again to configure the destination device to provide access to the data in its respective relative locations on the destination device.

Abstract: A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.

Abstract: A BIOS boot and update failover process is provided. A computing system can include flash storage on which the BIOS is stored, an embedded controller and an NVMe drive. After the BIOS successfully performs a boot process, a failover module can be executed to create a BIOS namespace on an NVMe namespace and then store a copy of the BIOS on the NVMe namespace. The failover module can also create a device path that identifies where the copy of the BIOS is stored on the NVMe namespace and store the device path on the embedded controller. The embedded controller can be configured to detect when the BIOS on the flash storage fails to initiate a subsequent boot process and, in response, employ the device path to locate and load the copy of the BIOS from the NVMe namespace to thereby cause the computing system to be booted.

Abstract: A method, a system, and a computer product for connecting computing components are disclosed. One or more data input and output properties of a data processing component in a plurality of data processing components are determined. At least one of the data input properties and data output properties of the data processing component are configured for connection of the data processing component to another data processing component in the plurality of data processing components in the data processing pipeline using a predetermined data pipeline connection topology. Using the predetermined data pipeline connection topology, the data processing component and another data processing component are dynamically connected using the configured properties.

Abstract: A flash memory initialization method executed by a flash memory initialization device to initialize a flash memory device having a flash memory and a flash memory controller includes: determining an acceptable maximum number N of candidate addresses; determining a number M of different capacity sizes; classifying the candidate addresses into M portions; determining a difference value between two address values of any two adjacent addresses among the m-th portion of candidate addresses; determining multiple address values of the m-th portion of candidate addresses according to the difference value; and determining actual addresses of the m-th portion of candidate addresses according to the multiple address values; and controlling the flash memory controller to write the boot up information into at least one storage location corresponding to at least one of the m-th portion of candidate addresses according to the actual addresses.

Abstract: The invention relates to a device (100) for performing at least one medical action at a human or animal body; wherein the device (100) comprises an energy source (107) and a computer (103); wherein the computer (103) a) comprises a first erasable non-volatile memory (104), and b) is configured for performing at least one application, the application being configured i) to control the medical action, and ii) to prioritize the medical action over a memory cleaning called by a wear leveling. Furthermore, the invention relates to a process, comprising operating the device (100) in consecutive cycles or tasks; to a use of a wear leveling algorithm and a prioritizing algorithm; and to a use of the device (100) in a treatment of a diabetes mellitus.

Abstract: An aspect of implementing globally optimized partial deduplication of storage objects includes gathering pages that share a common feature, dividing the pages into groups based on commonality with corresponding representative pages, where each is assigned as a representative dedupe page for the corresponding groups. For each group in the groups of pages, an aspect also includes writing the pages to a corresponding physical container.

Abstract: A processing device in a memory system receives requests to perform a plurality of memory access operations at a memory device configured with a zone namespace having a plurality of zones. The memory device includes a plurality of planes, wherein each zone of the plurality of zones is associated with a separate plane of the plurality of planes. The processing device further concurrently performs a first memory access operation of the plurality of memory access operations on first data stored in a first zone of the plurality of zones and a second memory access operation of the plurality of memory access operations on second data stored in a second zone of the plurality of zones, wherein the first zone is associated with a first plane of the plurality of planes, and wherein the second zone is associated with a second plane of the plurality of planes.