Patents Examined by Tammara R. Peyton
  • Patent number: 10558422
    Abstract: According to one embodiment, a media system communicates with an aggregate device that includes multiple media output devices. When providing media data for presentation, the system adjusts for device clock drift by resampling the media data provided to a media output device based at least in part on a device clock rate difference between a device clock of one of the media output devices and a device clock of another of the media output devices.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: February 11, 2020
    Assignee: Apple Inc.
    Inventors: Jeffrey C. Moore, William George Stewart, Gerhard Lengeling
  • Patent number: 10558609
    Abstract: In an embodiment, an electronic device for filtering an incoming digital signal includes several elementary filtering modules that include an elementary input configured to receive an incident elementary signal extracted from an incoming signal, an elementary output, and a dedicated capacitive circuit. The device further includes a resistive circuit common to all the elementary filtering modules and configured for cooperating with the capacitive circuit of each elementary filtering module in such a manner as to filter, on the respective elementary output, pulses of the incident elementary signal having a first voltage level and a duration less than a time constant and to deliver a filtered elementary signal on the elementary output.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: February 11, 2020
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: François Tailliet, Chama Ameziane El Hassani
  • Patent number: 10552054
    Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward W. Chencinski, Bruce Ratcliff, Eric N. Lais, Michael James Becht, Matthias Klein
  • Patent number: 10552089
    Abstract: A data processing method to improve data storage flexibility includes receiving, by a first storage management device, a data write request generated by a host, where the host is provided with the first storage management device, determining, by the first storage management device according to the data write request, scheduling information corresponding to the data write request, where the data write request includes to-be-written data, and the scheduling information corresponding to the data write request indicates a distributed storage pool, or a local storage device of the host, and processing, by the first storage management device, the to-be-written data according to the scheduling information corresponding to the data write request.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: February 4, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Weihua Shan, Jia Li, Yang Dong
  • Patent number: 10552366
    Abstract: Some embodiments include a method of communication between a master device and N slave devices on a synchronous data bus. The method includes selecting a slave device from among the N slave devices using a selection channel, where the master device and the N slave devices are coupled in series through the selection channel. The method also includes transmitting data between the master device and the selected slave device using a transmission channel, where the master device and the N slave devices are coupled in parallel through the transmission channel.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: February 4, 2020
    Assignee: STMICROELECTRONICS (GRAND OUEST) SAS
    Inventor: Thierry Biniguer
  • Patent number: 10552357
    Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Zuoguo J. Wu, Mahesh Wagh, Debendra Das Sharma, Gerald S. Pasdast, Ananthan Ayyasamy, Xiaobei Li, Robert G. Blankenship, Robert J. Safranek
  • Patent number: 10552354
    Abstract: Managing starvation in a distributed arbitration scheme including sending, by a starved local arbiter, a starvation message toward a head arbiter, wherein the starvation message comprises an identifier of the starved local arbiter and a request for resources to transfer data to a destination, wherein the requested resources comprise a destination token and a bus slot; receiving, by a neighboring local arbiter, the starvation message, wherein the neighboring local arbiter is between the starved local arbiter and the head arbiter; if the neighboring local arbiter currently has the resources requested in the starvation message: marking, by the neighboring local arbiter, the requested resources with the identifier of the starved local arbiter.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Howe, Charles F. Marino, Harrison M. McCreary, Mark L. Rudquist
  • Patent number: 10545900
    Abstract: In various embodiments, methods and systems are provide for detecting a physical configuration of a device based on sensor data from one or more configuration sensors. The physical configuration includes a position of a first display region of the device with respect to a second display region of the device, where the position is physically adjustable. A configuration profile is selected from a plurality of configuration profiles based on the detected physical configuration of the device. Each configuration profile is a representation of at least one respective physical configuration of the device. An interaction mode corresponding to the selected configuration profile is activated, where the interaction mode includes a set of mode input/output (I/O) features available while the interaction mode is active. Device interfaces of the device are managed using at least some mode I/O features in the set of mode I/O features based on the activating of the interaction mode.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: January 28, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Aaron Mackay Burns, Riccardo Giraldi, Christian Klein, Roger Sebastian Kevin Sylvan, John Benjamin George Hesketh, Scott G Wade
  • Patent number: 10545610
    Abstract: A tablet computer is provided, which includes a sensor section operable to detect positional input by a human operator and output a positional input signal; a display, laid over the sensor section, operable to receive and display a video signal; and a processor, coupled to a memory storing programs for running an operating system (OS) and executing software loaded to the memory, the processor being operable to receive and process the positional input signal from the sensor section and to output a video signal of the OS and the software to the display. The tablet computer further includes a sensor signal filter capable of selectively communicating the positional input signal from the sensor section to the processor, to a separate external processor, or to neither the processor nor the separate external processor; and a display switch capable of coupling the display to the processor or to the separate external processor.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: January 28, 2020
    Assignee: Wacom Co., Ltd.
    Inventors: Konrad Pollmann, Michael Thompson
  • Patent number: 10540312
    Abstract: Various examples of the present technology provide a cluster-architecture to support a scalable pooled-NVMe storage box that can be shared among a scalable number of nodes. The scalable pooled-NVMe storage box comprises NVMe drives, one or more switches and one or more switch ports. The number of NVMe drives in the scalable scalable-pooled-NVMe storage box can be scaled up or down based upon a number of nodes that need to share the scalable pooled-NVMe storage box.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: January 21, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventor: Ching-Chih Shih
  • Patent number: 10534561
    Abstract: A storage apparatus and a storing method are provided. The storage apparatus includes one or more storage devices, an interface expander and a master controller. The storage device includes a storage module, a storage control circuit and a ready/busy pin. The storage control circuit outputs an operational state signal according to an operational state of the storage module through the ready/busy pin. The master controller outputs an interface signal to indicate the interface expander to provide the operational state signal. The interface expander detects the ready/busy pin of the storage device to receive and transmit the operational state signal from the storage device to the master controller according to the interface signal. The master controller determines whether the storage device is in a busy state or a ready state according to the operational state signal, and accordingly outputs a control signal to control operations of the storage devices.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: January 14, 2020
    Assignee: ADATA TECHNOLOGY CO., LTD.
    Inventors: Kuo-Hua Yuan, Kuo-Chung Liao
  • Patent number: 10521378
    Abstract: An adaptive interface storage device. In some embodiments, the adaptive interface storage device includes: a rear storage interface connector; an adaptable circuit connected to the rear storage interface connector; a first multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the first multiplexer. The adaptive interface storage device may be configured to operate in a first state or in a second state. The adaptive interface storage device may be configured: in the first state, to present a device side storage interface according to a first storage protocol at the front storage interface connector, and in the second state, to present a device side storage interface according to a second storage protocol, different from the first storage protocol, at the front storage interface connector.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: December 31, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Stephen G. Fischer, Sompong Paul Olarig
  • Patent number: 10512410
    Abstract: A method, system and computer readable media for a BMI using a fixed decoder based on ratios of different frequency bands, making the decoder robust, less jittery, and resistant to artifacts. The fixed decoder can be configured to use a limited subset of available channels. The decoder can therefore be optimized for each human subject (frequency bands to use, ratios to process the received signals, which channels, weights, etc.) and then fixed. Output from the fixed decoder can be provided to a training program that implements specific feedback and training parameters, thereby enabling subjects to learn to control devices rapidly, as well as consolidate this control. The training program provides continuous feedback of the current transformation being output by the fixed decoder in conjunction with feedback of the past transformations (e.g., up to a second before) and saliency of the feedback when goals of the task are achieved.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: December 24, 2019
    Assignee: FUNDAÇÄO D. ANNA SOMMER CHAMPALIMAUD E DR. CARLOS MONTEZ CHAMPALIMAUD
    Inventors: Nuno Loureiro, Vitor B. Paixão, Rui M.Costa, Fernando Santos
  • Patent number: 10515044
    Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. An apparatus includes a serial bus, and an originating device and destination device coupled to the serial bus. The originating device may be configured to generate a first virtual GPIO packet that carries a payload representative of signaling state of physical GPIO in the originating device, generate a second virtual GPIO packet that carries a payload representative of an event generated by a processor in the originating device, and transmit the first and second virtual GPIO packets on the serial bus. The destination device may be configured to receive the second virtual GPIO packet from the serial bus, and communicate the event to a processor of the destination device or modify signaling state of physical GPIO in the destination device in accordance with the payload of the second virtual GPIO packet.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: December 24, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Dominic Wietfeldt, Radu Pitigoi-Aron, Lalan Jee Mishra
  • Patent number: 10515032
    Abstract: A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express (PCIe) compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Zhiming Li, Xingping Ruan, Xiao Hu, Terrence Trausch, Robert Pebly, Xiang Zhou, Jie Yan
  • Patent number: 10503687
    Abstract: Described herein are enhancements for managing multi-host Peripheral Component Interconnect Express (PCIe) switching. In one implementation, a system includes one or more PCIe devices and a PCIe switch configured to receive a first interrupt corresponding to a first interrupt vector from a PCIe device, wherein the first interrupt vector comprises at least a virtual address and a first data value. The switch is further configured to translate the first interrupt vector into a second interrupt vector, wherein the second interrupt vector comprises a second address and a second data value, and transfer a second interrupt using the second interrupt vector to a host of a plurality of hosts that corresponds to the second interrupt vector.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 10, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Berck Nash, Michael Walker, Randall Hess
  • Patent number: 10496561
    Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked memory are disclosed. A computing system includes a host processor die and multiple vertically stacked memory dies. The host processor die generates memory access requests for the data stored in the multiple memory array banks in the memory dies. At least one memory die uses an on-die network switch with a programmable routing table for routing packets corresponding to the generated memory requests. Routes use both vertical hops and horizontal hops to reach the target memory array bank and to avoid any congested or failed resources along the route. The vertically stacked memory dies use through silicon via interconnects and at least one via does not traverse through all of the memory dies. Accordingly, the host processor die does not have a direct connection to one or more of the multiple memory dies.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 3, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David A. Roberts, Sudhanva Gurumurthi
  • Patent number: 10481924
    Abstract: One or more examples provide techniques to dynamically manage serial port interface(s) of virtualization software executing in a host device. In an example, a method of managing a serial port interface of virtualization software executing on a host device includes initializing a serial port interface of the host device and examining a headless flag to determine if the host device is headless. If the headless flag is set, the method includes setting one or more serial port options to a default value, where a first serial port option connects a direct console user interface (DCUI) service to the serial port interface.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: November 19, 2019
    Assignee: VMware, Inc.
    Inventor: Nagib Gulam
  • Patent number: 10471204
    Abstract: A medical system includes an input assembly for receiving one or more user inputs. The input assembly includes at least one slider assembly for providing an input signal. Processing logic receives the input signal from the input assembly and provides a first output signal and a second output signal. A display assembly is configured to receive, at least in part, the first output signal from the processing logic and render information viewable by the user. The second output signal is provided to one or more medical system components. The information rendered on the display assembly may be manipulatable by the user and at least a portion of the information rendered may be magnified.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: November 12, 2019
    Assignee: DEKA PRODUCTS LIMITED PARTNERSHIP
    Inventors: Kevin L. Grant, Douglas J. Young, Matthew C. Harris
  • Patent number: 10474496
    Abstract: A method is disclosed for dynamic multitasking in a storage system, the storage system including a first storage server configured to execute a first I/O service process and one or more second storage servers, the method comprising: detecting a first event for triggering a context switch; transmitting to each of the second storage servers an instruction to stop transmitting internal I/O requests to the first I/O service process, the instruction including an identifier corresponding to the first I/O service process, the identifier being arranged to distinguish the first I/O service process from other first I/O service processes that are executed by the first storage server concurrently with the first I/O service process; deactivating the first I/O service process by pausing a frontend of the first I/O service process, and pausing one or more I/O providers of the first I/O service process; and executing a first context switch between the first I/O service process and a second process.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: November 12, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Lior Kamran, Amitai Alkalay, Zvi Schneider