Abstract: A micromechanical device comprising one or more electronically movable structure sets comprising for each set a first electrode supported on a substrate and a second electrode supported substantially parallel from said first electrode. Said second electrode is movable with respect to said first electrode whereby an electric potential applied between said first and second electrodes causing said second electrode to move relative to said first electrode a distance X, (X), where X is a nonlinear function of said potential, (V). Means are provided for linearizing the relationship between V and X.

Abstract: A pixel cell having a substrate with a isolation channel formed of higher carbon concentrate such as SiC or carbonated silicon. The channel comprising SiC or carbonated silicon is provided over the substrate of the pixel cell to reduce the dark current leakage.

Abstract: An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.

Abstract: A light-emitting element using GaN. On a substrate (10), formed are an SiN buffer layer (12), a GaN buffer layer (14), an undoped GaN layer (16), an Si-doped n-GaN layer (18), an SLS layer (20), an undoped GaN layer (22), an MQW light-emitting layer (24), an SLS layer (26), and a p-GaN layer (28), forming a p electrode (30) and an n electrode (32). The MQW light-emitting layer (24) has a structure in which InGaN well layers and AlGaN barrier layers are alternated. The Al content ratios of the SLS layers (20, and 26) are more than 5% and less than 24%. The In content ratio of the well layer in the MQW light-emitting layer (24) is more than 3% and less than 20%. The Al content ratio of the barrier layer is more than 1% and less than 30%. By adjusting the content ratio and film thickness of each layer to a desired value, the light luminous efficiency for wavelength of less than 400 nm is improved.

Abstract: A semiconductor forming transistors on a semiconductor substrate includes a low concentration source/drain region formed in the semiconductor substrate, a high concentration source/drain region formed in the source/drain region, a gate electrode formed on the substrate through gate oxide film, a P type body region formed under the gate electrode and placed between the source/drain regions and, plug contact portions contacting the source/drain region and arranged in plural, and a source/drain electrode connecting to the source/drain region with contact through the contact portions.

Abstract: A fuse link is formed between first and second terminals. The first and second terminals and fuse link have a polysilicon layer and a layer formed on the polysilicon layer and containing a metal element. At least a portion of the fuse link is an amorphous silicon layer.

Abstract: Gallium nitride material-based semiconductor structures are provided. In some embodiments, the structures include a composite substrate over which a gallium nitride material region is formed. The gallium nitride material structures may include additional features, such as strain-absorbing layers and/or transition layers, which also promote favorable stress conditions. The reduction in stresses may reduce defect formation and cracking in the gallium nitride material region, as well as reducing warpage of the overall structure. The gallium nitride material-based semiconductor structures may be used in a variety of applications such as transistors (e.g. FETs) Schottky diodes, light emitting diodes, laser diodes, SAW devices, and sensors, amongst others devices.

Abstract: The semiconductor device comprises a resistance element 26 formed of polysilicon film formed on a silicon substrate 10, which includes a resistor part 26a having a resistance value set at a prescribed value, contact parts 26b formed on both sides of the resistor part 26a and connected to a line for applying a fixed potential, and a heat radiation part 26c connected to the contact part 26b, whereby the semiconductor device can include the resistance element having a small parasitic capacitance and good heat radiation.

Abstract: Semiconductor device-based chemical sensors and methods associated with the same are provided. The sensors include regions that can interact with chemical species being detected. The chemical species may, for example, be a component of a fluid (e.g., gas or liquid). The interaction between the chemical species and a region of the sensor causes a change in a measurable property (e.g., an electrical property) of the device. These changes may be related to the concentration of the chemical species in the medium being characterized.

Abstract: A transistor having at least one of a source electrode and a drain electrode being formed of a porous film is described. The transistor maintains its characteristics even after being subjected to a high temperature and high humidity environment. The transistor may be used in a circuit board, a display and electronic equipment.

Abstract: A semiconductor apparatus comprises a gate electrode, a gate insulating layer, a drift region of a first conductivity type formed over a semiconductor substrate of the first conductivity type, a base region of a second conductivity type formed over the drift region, a source region of the first conductivity type formed on the base region and a column region formed in the drift region under the base region, the column region being divided into a plurality of divided portions in depth direction.

Abstract: A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and forming a gap in a buried N-type doped layer formed in the P-wells, the is gap aligned under a contact to the P-well. The buried P-type doped layer and gap in the buried N-type doped layer allow a low resistance hole current path around parasitic bipolar transistors of the CMOS transistors.

Abstract: A memory system is disclosed that includes a set of non-volatile storage elements. Each of said non-volatile storage elements includes source/drain regions at opposite sides of a channel in a substrate and a floating gate stack above the channel. The memory system also includes a set of shield plates positioned between adjacent floating gate stacks and electrically connected to the source/drain regions for reducing coupling between adjacent floating gates. The shield plates are selectively grown on the active areas of the memory without being grown on the inactive areas. In one embodiment, the shield plates are epitaxially grown silicon positioned above the source/drain regions.

Abstract: An InGaN active layer is formed on a sapphire substrate. A p-side electrode is formed on the InGaN active layer to supply an electric current to this InGaN active layer. The p-side electrode includes {circle around (1)} an Ni layer for forming an ohmic contact with a p-GaN layer, {circle around (2)} an Mo layer having a barrier function of preventing diffusion of impurities, {circle around (3)} an Al layer as a high-reflection electrode, {circle around (4)} a Ti layer having a barrier function, and {circle around (5)} an Au layer for improving the contact with a submount on a lead frame. The p-side electrode having this five-layered structure realizes an ohmic contact and high reflectance at the same time.

Abstract: In a solid-state imaging device in which a N-type photoelectric conversion region is formed in a P?-type well region, a light-blocking film and a transparent conductive film are formed on the N-type photoelectric conversion region with a second interlayer insulation film interposed therebetween. By applying a negative voltage to the light-blocking film and the transparent conductive film, a P++-type inversion region is formed in a topmost part of the N-type photoelectric conversion region.

Abstract: Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

Abstract: At an element formation surface side of a p-type Si substrate, a digital circuit and an analog circuit are provided. The analog circuit includes a p-type well and n-type wells formed at the element formation surface side of the p-type Si substrate. The analog circuit includes a deep n-type well located closer to the bottom side of the p-type Si substrate than the p-type well, so as to isolate the p-type well from a bottom-side region of the p-type Si substrate. The deep n-type well includes a first deep n-type well. The deep n-type well includes a second deep n-type well located closer to the bottom side of the p-type Si substrate than the first deep n-type well, and having an n-type impurity concentration, which is different from the first deep n-type well.

Abstract: An insulating tube includes a underlying insulating film, a first sidewall insulating film disposed on the underlying insulating film, a second sidewall insulating film disposed on the underlying insulating film, opposite to the first sidewall insulating film so as to provide a cavity between the first and second sidewall insulating films having the same height as the first sidewall insulating film, and an upper insulating film provided over the first and second sidewall insulating films.

Abstract: The present invention provides a method and apparatus for using light emitting diodes for curing and various solid state lighting applications. The method includes a novel method for cooling the light emitting diodes and mounting the same on heat pipe in a manner which delivers ultra high power in UV, visible and IR regions. Furthermore, the unique LED packaging technology of the present invention utilizes heat pipes that perform very efficiently in very compact space. Much more closely spaced LEDs operating at higher power levels and brightness are possible because the thermal energy is transported in an axial direction down the heat pipe and away from the light-emitting direction rather than a radial direction in nearly the same plane as the “p-n” junction.

Abstract: An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.