Abstract: A MAC operating device comprising a plurality of operation circuits respectively including an operation capacitor and a plurality of switches; and a division capacitor, wherein one end of the operation capacitor is respectively connected to a first operation switch connected to an input terminal and a first reset switch connected to a ground terminal, and the other end of the operation capacitor is connected to both a second operation switch connected to a division capacitor and a second reset switch connected to the ground terminal is provided.

Abstract: The present disclosure relates to a neuron for an artificial neural network. The neuron includes: a first dot product engine operative to: receive a first set of weights; receive a set of inputs; and calculate the dot product of the set of inputs and the first set of weights to generate a first dot product engine output. The neuron further includes a second dot product engine operative to: receive a second set of weights; receive an input based on the first dot product engine output; and generate a second dot product engine output based on the product of the first dot product engine output and a weight of the second set of weights. The neuron further includes an activation function module arranged to generate a neuron output based on the second dot product engine output. The first dot product engine and the second dot product engine are structurally or functionally different.

Abstract: Hardware for implementing a Deep Neural Network (DNN) having a convolution layer, the hardware comprising a plurality of convolution engines each configured to perform convolution operations by applying filters to data windows, each filter comprising a set of weights for combination with respective data values of a data window; and one or more weight buffers accessible to each of the plurality of convolution engines over an interconnect, each weight buffer being configured to provide weights of one or more filters to any of the plurality of convolution engines; wherein each of the convolution engines comprises control logic configured to request weights of a filter from the weight buffers using an identifier of that filter.

Abstract: Techniques of facilitating improved computational efficiency in Variational Quantum Eigensolver calculations by quantum computing devices. In one example, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components can comprise: a distribution component; and a feedback component. The distribution component can set a Pauli-dependent sample budget for a Pauli term of an operator to unevenly distribute a total sample budget for evaluating an expected value of the operator among a plurality of Pauli terms composing the operator. The plurality of Pauli terms can comprise the Pauli term. The feedback component can evaluate compatibility between a prescreening variance for the Pauli term and a production variance of the Pauli term generated using the Pauli-dependent sample budget.

Abstract: Certain aspects of the present disclosure provide techniques for detecting errors in account numbers. One example method generally includes receiving, from a user device, an entered number associated with a user and determining, based on a first portion of the entered number, an entity associated with the entered number. The method further includes obtaining, from an account number database, a plurality of account numbers associated with the entity and generating, from the plurality of account numbers, an account number matrix. The method further includes attempting to solve a multiplication equation of the account number matrix, wherein a solution of the multiplication equation is a vector of constants, upon determining a solution to the multiplication equation, determining whether the entered vector is a valid number for the entity and upon determining the entered vector is a valid number for the entity, storing the entered number in the account number database.

Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

Abstract: Aspects for neural network operations with floating-point number of short bit length are described herein. The aspects may include a neural network processor configured to process one or more floating-point numbers to generate one or more process results. Further, the aspects may include a floating-point number converter configured to convert the one or more process results in accordance with at least one format of shortened floating-point numbers. The floating-point number converter may include a pruning processor configured to adjust a length of a mantissa field of the process results and an exponent modifier configured to adjust a length of an exponent field of the process results in accordance with the at least one format.

Abstract: Embodiments of apparatus and method for matrix multiplication using processing-in-memory (PIM) are disclosed. In an example, an apparatus for matrix multiplication includes an array of tiles that each include one or more PIM blocks. A PIM block may include a hybrid-mode PIM block that may be configured into a digital mode or an analog mode. The PIM block configured into digital mode may perform operations associated with depth-wise (DW) convolution. On the other hand, a PIM block configured into analog mode may perform operations associated with point-wise (PW) convolution. A controller may be used to configure the PIM block into either digital mode or analog mode, depending on the computations.

Abstract: A method, computer readable medium, and processor are disclosed for performing matrix multiply and accumulate (MMA) operations. The processor includes a datapath configured to execute the MMA operation to generate a plurality of elements of a result matrix at an output of the datapath. Each element of the result matrix is generated by calculating at least one dot product of corresponding pairs of vectors associated with matrix operands specified in an instruction for the MMA operation. A dot product operation includes the steps of: generating a plurality of partial products by multiplying each element of a first vector with a corresponding element of a second vector; aligning the plurality of partial products based on the exponents associated with each element of the first vector and each element of the second vector; and accumulating the plurality of aligned partial products into a result queue utilizing at least one adder.

Abstract: In one embodiment, a method of simulating an operation of an artificial neural network on a binary neural network processor includes receiving a binary input vector for a layer including a probabilistic binary weight matrix and performing vector-matrix multiplication of the input vector with the probabilistic binary weight matrix, wherein the multiplication results are modified by simulated binary-neural-processing hardware noise, to generate a binary output vector, where the simulation is performed in the forward pass of a training algorithm for a neural network model for the binary-neural-processing hardware.

Abstract: A computer implemented method for speeding up execution of a convex optimization operation one or more quadratic complexity operations to be performed by an analog crossbar hardware switch, and identifying one or more linear complexity operations to be performed by a CPU. At least one of the quadratic complexity operations is performed by the analog crossbar hardware, and at least one of the linear complexity operations is performed by the CPU. An iteration of an approximation of a solution to the convex optimization operation is updated by the CPU.

Abstract: Techniques for computing matrix operations for arbitrarily large matrices on a finite-sized hybrid analog-digital matrix processor are described. Techniques for gain adjustment in a finite-sized hybrid analog-digital matrix processor are described which enable the system to obtain higher energy efficiencies, greater physical density and improved numerical accuracy. In some embodiments, these techniques enable maximization of the predictive accuracy of a GEMM-based convolutional neural network using low-precision data representations.

Abstract: An adaptive processor implements partial updates when it adjusts weights to optimize adaptation criteria in signal estimation, parameter estimation, or data dimensionality reduction algorithms. The adaptive processor designates some of the weights to be update weights and the other weights to be held weights. Unconstrained updates are performed on the update weights, whereas updates to the set of held weights are performed within a reduced-dimensionality subspace. Updates to the held weights and the update weights employ adapt-path operations for tuning the adaptive processor to process signal data during or after tuning.

Abstract: A computer-implemented method may include retrieving, via a remote data bus from a data store remote from a hardware accelerator to a local memory device (LMD) included in the hardware accelerator, (1) a filter matrix comprising a set of filter vectors corresponding to a filter location included in each of a set of filters of a convolutional layer of an artificial neural network (ANN), and (2) an activation matrix comprising a primary and a secondary set of activation vectors, each activation vector included in an activation volume inputted into the convolutional layer. The method may also include directing a hardware matrix multiplication unit (MMU) included in the hardware accelerator and communicatively coupled to the LMD via a local data bus, to execute a matrix multiplication operation (MMO) using the filter matrix and the activation matrix.

Abstract: Aspects include a compute array of a processor with mixed-precision numerical linear algebra support. A first precision and a first shape of a first input matrix and a second precision and a second shape of a second input matrix to the compute array are determined. A plurality of linear algebra operations is repeated in parallel within the compute array to update a result matrix in an accumulator register based on the first input matrix, the second input matrix, and a number of rank updates of the result matrix to store in the accumulator register.

Abstract: A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents.

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

Abstract: Provided are systems, methods, and integrated circuits for a neural network processing system. In various implementations, the system can include a first array of processing engines coupled to a first set of memory banks and a second array of processing engines coupled to a second set of memory banks. The first and second set of memory banks be storing all the weight values for a neural network, where the weight values are stored before any input data is received. Upon receiving input data, the system performs a task defined for the neural network. Performing the task can include computing an intermediate result using the first array of processing engines, copying the intermediate result to the second set of memory banks, and computing a final result using the second array of processing engines, where the final result corresponds to an outcome of performing the task.

Abstract: An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.