Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.

Abstract: A memory device includes a command decoder that implements security logic to detect a command sequence to read a security region of a memory array with continuous encrypted data and to output/input specific contexts for the data. Output/input of specific contexts can be during a dummy cycle to achieve greater performance. A host interfacing can, for example, execute a single command to both get the encrypted data and specific contexts that were used to encrypt the data. Our technology can implement transferring data on the system bus in ciphertext and encrypted by a different Nonce or a different session key than used in a previous transfer operation. In this way, data will be represented with different ciphertext on the bus at different sessions; thereby defending against a replay attack.

Abstract: Performing a tune-up procedure on a storage device including determining, during a boot process, that a first storage device is available for a tune-up procedure, wherein the tune-up procedure prepares the first storage device for use after being offline; reserving the first storage device to perform the tune-up procedure, wherein reserving the first storage device prevents another system from performing the tune-up procedure on the first storage device; and executing the tune-up procedure on the first storage device.

Abstract: An Adaptive Memory Mirroring Performance Accelerator (AMMPA) includes a centralized transaction handling block that dynamically maps the most frequently accessed memory regions into faster access memory. The technique creates shadow copies of the most frequently accessed memory regions in memory devices associated with lower latency. The regions for which shadow copies are provided are updated dynamically based on use, and the technique flexible for different memory hierarchies.

Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.

Abstract: A data storage system includes multiple head nodes and data storage sleds. Volume data is replicated between a primary and one or more secondary head nodes for a volume partition and is further flushed to a set of mass storage devices of the data storage sleds. Volume metadata is maintained in a primary and one or more secondary head nodes for a volume partition and is updated in response to volume data being flushed to the data storage sleds. Also, the primary and secondary head nodes store check-points of volume metadata to the data storage sleds, wherein in response to a failure of a primary or secondary head node for a volume partition, a replacement secondary head node for the volume partition recreates a secondary replica for the volume partition based, at least in part, on a stored volume metadata checkpoint.

Abstract: A memory system according to an embodiment includes a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks. The memory controller includes first and second tables, and first and second storage areas. The first table is managed in units of map segments. The second table includes first entries associated with a plurality of map segments included in the first table. The first storage area is configured to store a change history of the first table. The second storage area is configured to store a physical address of a block that is a storage destination of a copy of a changed map segment and a change history of the second table.

Abstract: A data storage device whose controller is configured to apply a hash function to a logical address specified in a received host request to obtain a first portion of the corresponding physical address (e.g., the channel number or channel and die numbers). This feature of the controller enables the L2P table stored in the DRAM associated with the controller to have physical-address entries that contain therein only complementary second portions of the physical addresses, but not the first portions. Such shorter physical-address entries in the L2P table enable a corresponding beneficial reduction in the size of the DRAM and can further be leveraged to have optimized and aligned access to the L2P table in the DRAM.

Abstract: According to an embodiment, when receiving a read request designating a logical address range of a particular size or more from a host, a first circuit issues a plurality of first sub-commands, each of which is a sub-command for each first data unit, in order of logical addresses. A second circuit respectively adds serial numbers corresponding to the plurality of first sub-commands in the order of issuance. A plurality of third circuits respectively executes processing of specifying locations of the first data unit based on management information for the plurality of first sub-commands in a distributed manner. A fifth circuit reorders the plurality of first sub-commands in the logical address order based on the serial numbers after the processing by the plurality of third circuits. A sixth circuit executes a read operation on a first memory based on the plurality of first sub-commands reordered in the order of logical addresses.

Abstract: This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Abstract: A technique for managing a storage system involves determining, in response to a first write operation on a first data block on a persistent storage device, whether a first group of data corresponding to the first data block is included in a cache; updating the first group of data in the cache if it is determined that the first group of data is included in the cache; and adding the first group of data to an associated data set of the cache to serve as a first record. Accordingly, such a technique can associatively manage different types of cached data corresponding to a data block, thereby optimizing the system performance.

Abstract: An apparatus and/or system is described including a memory device including a memory range and a temporal data management unit (TDMU) coupled to the memory device to receive from an interface, the memory range and a temporal range corresponding to validity of data in the memory range, check the temporal range against a time and/or date value provided by a timer or clock to identify the data in the memory range as expired, and invalidate the data that is expired in the memory device. In some embodiments, the TDMU includes hardware logic that resides on a memory module with the memory device and is coupled to invalidate expired data when the memory module is decoupled from the interface. Other embodiments may be disclosed and claimed.

Abstract: Improvements are disclosed for “leveling” or averaging out more evenly the number of activate/precharge cycles seen by the rows of a memory component, so that one or more particular rows are not excessively stressed (relative to the other rows). In one embodiment, a memory controller includes remapping facilities arranged to move data stored in a physical row from RPK to RPK? and modify the mapping from logical row RLK while minimizing impact on normal read/write operations. Remapping operations may be scheduled relative to refresh or other maintenance operations. Remapping operations may be conditionally deferred so as to minimize performance impact.

Abstract: A solid state storage device includes a control circuit, a volatile memory and a non-volatile memory. The non-volatile memory is divided into a first area and a second area. After the host issues a write command and a write data, the control circuit monitors a data amount of the write data continuously stored into the non-volatile memory. Before the data amount of the write data continuously stored into the non-volatile memory reaches a predetermined amount, the write data is stored into plural buffering blocks of the first area in a first write mode. After the data amount of the write data continuously stored into the non-volatile memory reaches the predetermined amount, the write data is stored into plural storing blocks of the second area in a second write mode.

Abstract: Memory allocation for processing-in-memory operations, including: receiving, by an allocation module, a memory allocation request indicating a plurality of data structure operands for a processing-in-memory operation; determining a memory allocation pattern for the plurality of data structure operands, wherein the memory allocation pattern interleaves a plurality of component pages of a memory page across the plurality of data structure operands; and allocating the memory page based on the determined memory allocation pattern.

Abstract: Disclosed is a method for enhancing service quality of a solid state drive and the solid state drive, and the method includes the steps of obtaining a remaining storage resource corresponding to a write I/O request periodically, and determining a resource waiting time of the write I/O request based on a resource consumption rate of the write I/O request. The method also includes setting a maximum scheduling delay time for the write I/O request according to the resource waiting time of the write I/O request. The method also includes identifying a type of unprocessed I/O requests and obtaining an arrival time of the unprocessed I/O requests, and sorting the unprocessed I/O requests in combination with the maximum scheduling delay time. The method further includes processing the unprocessed I/O requests according to the sort of the unprocessed I/O requests.

Abstract: Provided are a method, an apparatus, and a memory controller coupled to a plurality of storage dies, wherein the memory controller implements logic to perform operations with respect to the storage dies, the operations comprising: maintaining a calendar based scheduling mechanism that is programmed by a firmware to support a quality of service scheduling in a solid state drive in which the memory controller is included; and determining, by a flash command scheduler, from the calendar based scheduling mechanism, which traffic class to service.

Abstract: Multiple logical-to-physical translation tables (L2PTTs) for data storage devices having indirection units of different sizes. In one embodiment, a data storage controller includes a memory interface configured to interface with a memory, the memory including a zoned namespace, the zoned namespace including a plurality of zones. The data storage controller includes a controller memory including two or more logical-to-physical translation tables (L2PTTs), and an electronic processor. The electronic processor is configured to receive data to be stored in a zone of the plurality of zones, determine whether the zone is an active zone, select, in response to determining that the zone is the active zone, a first L2PTT having a first indirection unit size, and select, in response to determining that the zone is not the active zone, a second L2PTT having a second indirection unit size.

Abstract: One example method of testing an electrical device comprises transmitting a data pattern to a memory device of the electrical device by a controller of the electrical device to provide a written data pattern to the memory device, wherein the data pattern replicates a resonant frequency of at least a portion of the electrical device, reading the written data pattern from the memory device with the controller, and comparing the written data pattern to the data pattern.

Abstract: An example non-transitory computer readable storage medium comprising instructions that when executed cause a processor of a computing device to: in response to a trigger of a system management mode (SMM), verify all processor threads have been pulled into the SMM; in response to a successful verification, enable write access to a non-volatile memory of the computing device via two registers, where the writing access is disabled upon booting of the computing device; and upon exiting the SMM, disable the write access via the two registers.