Abstract: A method of managing a storage system comprises detecting a reference to a first page in the storage system. The method also comprises creating a first candidate block for the first page based on the detecting. The first candidate block may comprise a continuous series of pages that begins with the first page. The method also comprises monitoring subsequent references to pages within the first candidate block. The method also comprises determining that the first candidate block meets a first set of hot-block requirements. The method also comprises relocating the first candidate block to a hot-block space in a buffer pool based on the determining, resulting in a first hot block.

Abstract: A storage device includes: a memory device including a map data block including mapping information between a logical address and a physical address; a buffer memory device for storing a block state table including block state information; and a memory controller for determining valid data of a source block among the plurality of memory blocks based on mapping information and block state information corresponding to the source block, and moving the valid data to open memory block. The memory controller may generate a valid page list in which information of the valid data is arranged in a stripe page unit according to an order of logical addresses, and control the memory device to move the valid data to the open memory block, based on the valid page list.

Abstract: Methods, systems, and devices for session-based memory operation are described. A memory system may determine that a logical address targeted by a read command is associated with a session table. The memory system may write the session table to a cache based on the logical address being associated with the session table. After writing the session table to the cache, the memory system may use the session table to determine one or more logical-to-physical (L2P) tables and write the one or more L2P tables to the cache. The memory system may use the L2L tables to perform address translation for logical addresses.

Abstract: Various embodiments set forth techniques for transactional allocation and deallocation of blocks in a block store. A first technique includes sending a first request that causes a non-persistent allocation of a block. The first technique also includes adding a first entry in a log recording the allocation as tentative, sending a second request that causes persistence of the allocation, and adding a second entry in a log recording the allocation as finalized. A second technique includes adding a first entry in a log recording a deallocation of a block, sending a first request that causes the deallocation of the block and causes the block to be unavailable for reallocation in a non-persistent manner, adding a second entry in the log recording that the deallocation is finalized, and sending a second request that causes the block to be made available for reallocation.

Abstract: A method for performing an operation of a memory arrangement, comprising receiving a command at a layer of a computer system, determining if the command received is one of a first command type or a second command type, determining a type of command that is able to be received and is capable of operation of the memory arrangement, comparing the type of command capable of operation of the memory arrangement and the received command at the layer, and converting the command received at the layer to a command type capable of operation of the memory arrangement when the type of command received at the layer is different than type of command that is able to be received and is capable of operation of the memory arrangement.

Abstract: A non-volatile storage device according to an embodiment of the present technology includes a storage section and a calculation section. The storage section includes a plurality of block sections each including a plurality of page sections into which data can be written independent of each other, the plurality of block sections being capable of collectively deleting the data written in the plurality of page sections. The calculation section calculates, on the basis of information about write conditions of the plurality of page sections included in the storage section, candidate addresses that are candidates of logical addresses of the data to be written into the plurality of page sections.

Abstract: An electronic device includes a memory controller having an improved operation speed. The memory controller includes a processor configured to generate commands for accessing data stored in a main memory, a scheduling circuit configured to store the commands and output the commands according to a preset criterion, and a filtering circuit configured to store information on an address of the main memory corresponding to a write command among the commands, provide a pre-completion response for the write command to the scheduling circuit upon receiving the write command, and provide the write command to the main memory.

Abstract: An example apparatus comprises a controller coupled to a non-volatile memory (NVM) device. The controller may be configured to cause a logical block address (LBA) to be stored in a first logical-to-physical (L2P) data structure in the NVM device and a physical block address (PBA) to be stored in a second L2P data structure in the NVM device The first L2P data structure and the second L2P data structure may have a same size associated therewith.

Abstract: Various embodiments described herein provide for operation of a memory sub-system based on a profile (also referred to herein as an operational profile) that causes the memory sub-system to have a specific set of operational characteristics. Additionally, some embodiments can provide dynamic switching between profiles based on a set of conditions being satisfied, such as current time of day or detection of a particular data input/out (I/O) pattern with respect to the memory sub-system.

Abstract: A predictive method for scheduling of the operations is described. The predictive method utilizes data generated from computing an expected lifetime of the individual files or objects within the container. The expected lifetime of individual files or objects can be generated based on machine learning techniques. Operations such as garbage collection are scheduled at an epoch where computational efficiencies are realized for performing the operation.

Abstract: The present technology relates to an electronic device. A storage device includes a memory device including pages, a buffer memory configured to store address mapping information including a mapping relationship between logical addresses provided from a host and physical addresses corresponding to the pages, first trim bitmap information including trim information of first logical address groups each including a first number of logical addresses having at least two of the logical addresses, and second trim bitmap information including trim information of second logical address groups each including a second number of logical addresses greater than the first number of the logical addresses, and a memory controller configured to change, based on a number of trim-requested logical addresses from the host, map states of the trim-requested logical addresses in one of the address mapping information, the first trim bitmap information, and the second trim bitmap information.

Abstract: Systems, methods, and devices dynamically configure non-volatile memories. Devices include non-volatile memories comprising a plurality of memory regions, each of the plurality of memory regions having a configurable bit density. Devices also include control circuitry configured to retrieve user partition configuration data identifying a plurality of bit densities for the plurality of memory regions, convert a received user address to a plurality of physical addresses based, at least in part, on the plurality of bit densities, compare the user address with the user partition configuration data, and select one of the plurality of physical addresses based, at least in part, on the comparison.

Abstract: A method, a computer program product, and a system for allocating a variable into storage class memory during compilation of a program. The method includes selecting a variable recorded in a symbol table during compilation and computing a variable size of the variable by analyzing attributes related to the variable. The method further includes computing additional attributes relating to the variable. The method also includes computing a control flow graph and analyzing the control flow graph and the additional attributes to determine an allocation location for the variable. The method further includes allocating the variable into a storage class memory based on the analysis performed.

Abstract: A memory system may transfer a reference write size for a memory device to a host, and, when receiving, from the host, a write request for first data having a size corresponding to a multiple of the reference write size, may directly write the first data to the memory device without caching the first data in a write cache.

Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device and a memory controller. The memory device may include first memory blocks and second memory blocks. The memory controller may be configured to control the memory device so that valid data stored in a victim block, among the first memory blocks, is stored in a target block, among the second memory blocks, based on a result of a comparison between an amount of valid data stored in the victim block and a reference value. Each of the first memory blocks may include memory cells each configured to store n bits, where n is a natural number of 2 or more. Each of the second memory blocks may include memory cells each configured to store m bits, where m is a natural number less than n.

Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: setting a GC starting threshold, wherein the GC starting threshold indicates a predetermined spare block number that is higher than a target spare block number of spare blocks maintained by a flash translation layer (FTL) of the flash memory; determining whether to start the GC operation according to a current number of spare blocks in the flash memory and the GC starting threshold; and performing the GC operation on a source block in the flash memory when the current number of spare blocks is lower than or equal to the GC starting threshold.

Abstract: One example method of testing an electrical device comprises transmitting a data pattern to a memory device of the electrical device by a controller of the electrical device to provide a written data pattern to the memory device, wherein the data pattern replicates a resonant frequency of at least a portion of the electrical device, reading the written data pattern from the memory device with the controller, and comparing the written data pattern to the data pattern.

Abstract: A data storage system includes a first memory, a second memory, and a memory controller. The memory controller transmits a first data segment from the first memory to the second memory according to an initial address, adds a first interval value to the initial address to generate a succeeding address, and updates a stream number. When the stream number has not reached a target stream number, the memory controller transmits second data segment from the first memory to the second memory according to the succeeding address, and updates the stream number. When the stream number has reached the target stream number, the memory controller sets the stream number to an initial value, adds an offset value to the initial address to update the succeeding address, and transmits a third data segment from the first memory to the second memory according to the updated succeeding address.

Abstract: The present invention provides a control method of a server, wherein the server includes a write buffer for temporarily storing data from an electronic device, the write buffer has a plurality of sectors, and the write buffer has a write pointer and a flush pointer; and the control method comprises: setting each sector to have one of a plurality of states comprising an empty state, a merging state, a need-flush state and a flushing state; and referring to a state of a specific sector indicted by the write pointer to determine if ignoring the specific sector to directly process a sector after the specific sector.

Abstract: A data processing method and a corresponding system are provided. The method is implemented by a processor and includes: obtaining a to-be-processed I/O request, where the to-be-processed I/O request may include a first address, and the first address is a logical address of to-be-read, to-be-written, or to-be-erased data in a target SSD; performing address translation on the to-be-processed I/O request based on an FTL mapping table, to translate the first address into a second address, where the second address is used to indicate a physical address of the to-be-read, to-be-written, or to-be-erased data in the target SSD, and the FTL mapping table may be used to record a translation relationship between physical addresses and logical addresses in the n SSDs; sending a to-be-processed I/O request obtained after address translation is performed; and after a sleep duration is preset, querying a processing result of the to-be-processed I/O request.