Abstract: One example method of testing an electrical device comprises transmitting a data pattern to a memory device of the electrical device by a controller of the electrical device to provide a written data pattern to the memory device, wherein the data pattern replicates a resonant frequency of at least a portion of the electrical device, reading the written data pattern from the memory device with the controller, and comparing the written data pattern to the data pattern.

Abstract: A method of managing a garbage collection (GC) operation on a flash memory includes: setting a GC starting threshold, wherein the GC starting threshold indicates a predetermined spare block number that is higher than a target spare block number of spare blocks maintained by a flash translation layer (FTL) of the flash memory; determining whether to start the GC operation according to a current number of spare blocks in the flash memory and the GC starting threshold; and performing the GC operation on a source block in the flash memory when the current number of spare blocks is lower than or equal to the GC starting threshold.

Abstract: The present invention provides a control method of a server, wherein the server includes a write buffer for temporarily storing data from an electronic device, the write buffer has a plurality of sectors, and the write buffer has a write pointer and a flush pointer; and the control method comprises: setting each sector to have one of a plurality of states comprising an empty state, a merging state, a need-flush state and a flushing state; and referring to a state of a specific sector indicted by the write pointer to determine if ignoring the specific sector to directly process a sector after the specific sector.

Abstract: A data storage system includes a first memory, a second memory, and a memory controller. The memory controller transmits a first data segment from the first memory to the second memory according to an initial address, adds a first interval value to the initial address to generate a succeeding address, and updates a stream number. When the stream number has not reached a target stream number, the memory controller transmits second data segment from the first memory to the second memory according to the succeeding address, and updates the stream number. When the stream number has reached the target stream number, the memory controller sets the stream number to an initial value, adds an offset value to the initial address to update the succeeding address, and transmits a third data segment from the first memory to the second memory according to the updated succeeding address.

Abstract: A data processing method and a corresponding system are provided. The method is implemented by a processor and includes: obtaining a to-be-processed I/O request, where the to-be-processed I/O request may include a first address, and the first address is a logical address of to-be-read, to-be-written, or to-be-erased data in a target SSD; performing address translation on the to-be-processed I/O request based on an FTL mapping table, to translate the first address into a second address, where the second address is used to indicate a physical address of the to-be-read, to-be-written, or to-be-erased data in the target SSD, and the FTL mapping table may be used to record a translation relationship between physical addresses and logical addresses in the n SSDs; sending a to-be-processed I/O request obtained after address translation is performed; and after a sleep duration is preset, querying a processing result of the to-be-processed I/O request.

Abstract: Aspects of the invention include systems and methods for tree style memory zone traversal. A non-limiting example computer-implemented method includes receiving, by a processor, a request from a requestor for available memory space in a main memory. The processor searches a plurality of memory zones in the main memory for the requested available memory space, wherein the memory zones are arranged in a ring structure and a separate tree structure, and the searching is based at least in part on both of the ring structure and the tree structure. In response to the processor finding the requested available memory space, processor allocates the found available memory space to the requestor.

Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for optimizing data storing. An exemplary method comprises: determining, by a host, a source physical storage to be released as a part of the garbage collection process and a destination physical storage to store data transferred from the source physical storage as a part of the garbage collection process; reading a logic address log corresponding to the data from the source physical storage to a controller, wherein the logic address log comprises logic addresses corresponding to the data; determining, by the controller, whether the logic addresses are valid; transferring the valid logic addresses to the host; and updating a mapping table with destination physical addresses according to the valid logic addresses, wherein: the mapping table is stored in the host, and the destination physical addresses correspond to the destination physical storage.

Abstract: A garbage collection method is provided and applied to a data storage device. The garbage collection method includes the following steps: selecting source blocks from data blocks, wherein a total number of valid data of the source blocks is larger than or equal to a predetermined data number of a block; copying valid data of a part of the source blocks into a destination block, wherein a total number of the valid data of the part of the source blocks is smaller than the predetermined data number; copying all or a part of valid data of remaining source blocks into the destination block; updating a logical to physical addresses mapping table based on a mapping information of the destination block; and recovering all or a part of the source blocks as spare blocks.

Abstract: A data merge method for a rewritable non-volatile memory module including multiple physical units is provided. The method includes: starting a first data merge operation, and selecting at least one first physical unit for executing the first data merge operation and at least one second physical unit for executing a second data merge operation from the physical units; reading first mapping information from the rewritable non-volatile memory module, and copying first valid data collected from the at least one first physical unit to at least one third physical unit in the physical units; identifying second valid data in the at least one second physical unit according to the first mapping information in the first data merge operation; and starting the second data merge operation, and copying the second valid data collected from the at least one second physical unit to at least one fourth physical unit in the physical units.

Abstract: An operation method is applied to a memory device. The memory device includes a plurality of memory tiles. The operation method includes following steps: utilizing a first wear leveling process to perform an intra-tile wear leveling on the plurality of memory tiles by a processor; and utilizing a second wear leveling process to perform an inter-tile wear leveling on the plurality of memory tiles by the processor.

Abstract: The present disclosure provides an operating method of a storage controller. The operating method includes receiving user data and environmental information, obtaining logical-characteristic information and physical-characteristic information, defining a current state, obtaining expectation values, and performing a write operation. User data and environmental information is received from a non-volatile memory. The current state may be defined based on the logical-characteristic information and the physical-characteristic information. Expectation values may be obtained based on policy information and the current state. The write operation may be performed on the user data through a physical stream corresponding to a maximum value among the expectation values.

Abstract: Techniques are provided for automated adaptive endurance tuning of solid-state storage media. For example, a storage control system tracks usage metrics associated with utilization of solid-state storage devices of a storage system, wherein the storage system comprises an amount of over-provisioned capacity allocated in the solid-state storage devices according to an over-provisioning factor. The storage control system determines a current endurance value of the data storage system based at least in part on the usage metrics, and compares the current endurance value to a target endurance value to determine if the current endurance value differs from the target endurance value.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a host configured to generate and output a host command and a host address and to receive and store host map data, a controller configured to store map data, generate an internal command in response to the host command, and map the host address to an internal address based on the map data, and a memory device configured to perform an operation in response to the internal command and the internal address, wherein the controller is configured to load, when the map data corresponding to the host address is not stored in the controller, new map data into a map data storage area storing map data that is identical to the host map data.

Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.

Abstract: A trim command processing method, a memory control circuit unit, and a memory storage apparatus are provided. The method includes: receiving a trim command from a host system, where the trim command is configured to indicate data stored in at least one logical address among a plurality of logical addresses can be erased; calculating a first data volume of data required to be programmed when a data trim operation is performed according to the trim command; and determining whether to perform a first trim operation or a second trim operation according to the first data volume.

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.

Abstract: The invention relates to a non-transitory computer program product, a method and an apparatus for managing garbage collection process. The non-transitory computer program product includes program code to: determine source blocks to be processed, wherein each source block includes an invalid page; program user data of valid pages in the source blocks, whose quantity is less than a total number of pages in one first-type physical block, into empty pages in a second-type physical block, wherein the total number of pages in one first-type physical block is greater than a total number of pages in one second-type physical block; and fill remaining empty pages in the second-type physical block with dummy values.

Abstract: The present application discloses a method for processing a deallocation command and a storage device thereof. The disclosed method includes the following steps: in response to receiving the deallocation command, obtaining an address range indicated by the deallocation command; and updating the table items of the deallocation table according to the address range indicated by the deallocation command. Embodiments of the present application can reduce the delay in processing the deallocation command and reduce the impact of processing the deallocation command on the processing bandwidth of the IO command.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data and may support a plurality of device streams. A SSD controller may manage reading and writing data to the flash memory, and may store a submission queue and a chunk-to-stream mapper. A flash translation layer may include a receiver to receive a write command, an LBA mapper to map an LBA to a chunk identifier (ID), stream selection logic to select a stream ID based on the chunk ID, a stream ID adder to add the stream ID to the write command, a queuer to place the chunk ID in the submission queue, and background logic to update the chunk-to-stream mapper after the chunk ID is removed from the submission queue.

Abstract: A memory apparatus for detecting false hits in a content-addressable memory (CAM) is disclosed. The memory apparatus includes a controller coupled to the CAM and a memory. The controller receives a search result including an address from the CAM, the address corresponding to a matching entry from a first set of data entries that matches a search tag. The controller provides a read address based on the address to the memory, which returns a second data entry from a second set of data entries corresponding to the read address. The controller receives the read data and generates an error detection result based on a comparison between the second data entry and the search tag.