Patents Examined by Telly Green
  • Patent number: 10008613
    Abstract: The present disclosure provides a TFT, an array substrate and a fabricating method thereof and a display device. The TFT includes a gate, an active layer, a first electrode and a second electrode, the first electrode is arranged at one side of the active layer, the second electrode is arranged at the other side of the active layer, the first electrode, the active layer and the second electrode forms a stacked structure, the gate is arranged to surround the stacked structure, and the gate and the stacked structure are insulated and separated from each other. Under fixed occupation area, the conductive channel of the TFT of the present disclosure has increased width, so drain current in saturation region is increased without impacting aperture ratio of a display panel, which further optimizes performance of the TFT and the array substrate, and improves display effect of the display device.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 26, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Shaozhuan Wang
  • Patent number: 9985180
    Abstract: A light emitting diode chip including a substrate and a light emitting diode element layer is provided. The substrate has a growth surface and a plurality of microstructures on the growth surface. An area of the growth surface occupied by the microstructures is A1 and an area of the growth surface not occupied by the micro-structures is A2, such that A1 and A2 satisfy the relation of 0.1?A2/(A1+A2)?0.5. The light emitting diode element layer is disposed on the growth surface of the substrate.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 29, 2018
    Assignees: SOUTHERN TAIWAN UNIVERSITY OF SCIENCE AND TECHNOLOGY, EVERLIGHT ELECTRONICS CO., LTD.
    Inventor: Ming-Lun Lee
  • Patent number: 9978805
    Abstract: Methods for forming image sensor structures are provided. The method includes forming an isolation structure in a substrate and forming a first light sensing region and a second light sensing region. The method further includes forming a first gate structure and a second gate structure, and the first gate structure and the second gate structure are positioned at a front side of the substrate. The method further includes forming a first source/drain structure adjacent to the first gate structure and a second source/drain structure adjacent to the second gate structure and forming an interlayer dielectric layer over the front side of the substrate. The method further includes forming a contact trench through the interlayer dielectric layer and forming a contact in the contact trench.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzu-Jui Wang, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Yuichiro Yamashita
  • Patent number: 9972806
    Abstract: A light-emitting element display device includes: a display area which has an organic insulating layer that is made of an organic insulating material; a peripheral circuit area which is disposed around the display area and which has the organic insulating layer; and a blocking area that is formed between the display area and the peripheral circuit area. The blocking area includes: a first blocking area configured by only one or a plurality of inorganic material layers between an insulating base substrate and an electrode layer which covers the display area and is formed continuously from the display area, and which configures one of two electrodes for allowing the light emitting area to emit the light; and a second blocking area including a plurality of layers configuring the first blocking area, and a light emitting organic layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: May 15, 2018
    Assignee: Japan Display Inc.
    Inventor: Masamitsu Furuie
  • Patent number: 9972704
    Abstract: A method for forming a semiconductor device comprises implanting a defined dose of protons into a semiconductor substrate and tempering the semiconductor substrate according to a defined temperature profile. At least one of the defined dose of protons and the defined temperature profile is selected depending on a carbon-related parameter indicating information on a carbon concentration within at least a part of the semiconductor substrate.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: May 15, 2018
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Johannes Georg Laven, Helmut Oefner, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 9960140
    Abstract: The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is Al based, the parts are joined through a joining layer containing Ni nanoparticles, whereby a good joining strength is obtained. Further, by using two joining layers (6, 8) including metal nanoparticles to sandwich metal foil (7) so as to form a joining layer and joining the same type or different types of surface metals (3-4) through this joining layer, it is possible to ease the thermal stress due to the difference in amounts of thermal expansion of joined members which have two surface metals.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: May 1, 2018
    Assignees: NIPPON STEEL & SUMITOMO METAL CORPORATION, WASEDA UNIVERSITY
    Inventors: Kohei Tatsumi, Shinji Ishikawa, Norie Matsubara, Masamoto Tanaka
  • Patent number: 9952693
    Abstract: The present invention provides a touch panel, including a lower substrate, an organic light-emitting component, disposed on the lower substrate, a nano silver sensing layer, disposed on the organic light emitting component, and an upper substrate, disposed on the nano silver sensing layer.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: April 24, 2018
    Assignee: TPK Touch Solutions Inc.
    Inventors: Chen-Yu Liu, Li-Wei Kung, Hsi-Chien Lin
  • Patent number: 9954039
    Abstract: An organic light emitting display device can include a substrate; an anode electrode on the substrate; an organic emitting layer on the anode electrode; a cathode electrode on the organic emitting layer; an auxiliary electrode connected to the cathode electrode; a bank provided on either side of the auxiliary electrode; and a partition spaced apart from the bank and provided on the auxiliary electrode, in which the partition includes a plurality of first partitions provided on the auxiliary electrode and spaced apart from each other, and the partition further includes a second partition provided on the plurality of first partitions, and a width of an upper surface of the second partition is larger than a width of a lower surface of the second partition.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: April 24, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jonghyeok Im, Eunah Kim
  • Patent number: 9953918
    Abstract: A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor link connected to an anode semiconductor region and a cathode semiconductor region; removing the first hard mask layer from the first substrate; depositing a second hard mask layer on the first substrate; patterning a photoresist on the first substrate and etching to form an opening in the semiconductor link; etching to remove portions of the second hard mask layer to expose a portion of a sidewall of the semiconductor link; removing the photoresist from the first substrate and the semiconductor link; and recessing the sidewalls of the semiconductor link forming first anti-fuse tip and second anti-fuse tip to form an anti-fuse with an opening between the first and second anti-fuse tips.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Patent number: 9947529
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 9947756
    Abstract: In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ting Li, Chih-Hao Chang, Sheng-Yu Chang, Jen-Hsiang Lu, Jyun-Yang Shen
  • Patent number: 9947667
    Abstract: A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 17, 2018
    Assignee: SK Hynix Inc.
    Inventors: Dong-Kyun Kang, Ho-Jin Cho
  • Patent number: 9947885
    Abstract: To provide a light-emitting element which uses a fluorescent material as a light-emitting substance and has higher luminous efficiency. To provide a light-emitting element which includes a mixture of a thermally activated delayed fluorescent substance and a fluorescent material. By making the emission spectrum of the thermally activated delayed fluorescent substance overlap with an absorption band on the longest wavelength side in absorption by the fluorescent material in an S1 level of the fluorescent material, energy at an S1 level of the thermally activated delayed fluorescent substance can be transferred to the S1 of the fluorescent material. Alternatively, it is also possible that the S1 of the thermally activated delayed fluorescent substance is generated from part of the energy of a T1 level of the thermally activated delayed fluorescent substance, and is transferred to the S1 of the fluorescent material.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Hiromi Seo, Tatsuyoshi Takahashi
  • Patent number: 9938133
    Abstract: According to an embodiment, a method of forming a MEMS transducer includes forming a transducer frame in a layer of monocrystalline silicon, where forming the transducer frame includes forming a support portion adjacent a cavity and forming a first set of comb-fingers extending from the support portion. The method of forming a MEMS transducer further includes forming a spring support from an anchor to the support portion and forming a second set of comb-fingers in the layer of monocrystalline silicon. The second set of comb-fingers is interdigitated with the first set of comb-fingers.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 10, 2018
    Assignee: INFINEON TECHNOLOGIES DRESDEN GMBH
    Inventors: Thoralf Kautzsch, Mohsin Nawaz, Alfons Dehe, Heiko Froehlich, Alessia Scire, Steffen Bieselt
  • Patent number: 9941122
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: April 10, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ik Oh, Daehyun Jang, Ha-Na Kim, Kyoungsub Shin
  • Patent number: 9941251
    Abstract: A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion extending laterally beyond a respective edge of the first die. The package further includes a first Thermal Interface Material (TIM) over and contacting a top surface of the first die, a heat dissipating lid having a first bottom surface contacting the first TIM, a second TIM over and contacting the second portion of the second die, and a heat dissipating ring having a portion over and contacting the second TIM. The heat dissipating lid and the heat dissipating ring are discrete components, and at least one of the heat dissipating lid or the heat dissipating ring has a plurality of fins and a plurality of recesses separating the plurality of fins from each other.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: April 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Szu-Po Huang, Kim Hong Chen, Shin-Puu Jeng
  • Patent number: 9941204
    Abstract: An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region including a second metal structure; and a middle region located between the first end region and the second end region. In accordance with the present application, the middle region of the anti-fuse includes at least a portion of the second metal structure that is located in a gap positioned between a bottom III-V compound semiconductor material and a top III-V compound semiconductor material. A high-k dielectric material liner separates the second metal structure from a portion of the first metal structure.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 9935070
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Hsuan-Ting Kuo, Tsung-Yuan Yu, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 9929350
    Abstract: A light-emitting element includes a light-emitting layer including a guest, an n-type host and a p-type host between a pair of electrodes, where the difference between the energy difference between a triplet excited state and a ground state of the n-type host (or p-type host) and the energy difference between a triplet excited state and a ground state of the guest is 0.15 eV or more. Alternatively, in such a light-emitting element, the LUMO level of the n-type host is higher than the LUMO level of the guest by 0.1 eV or more, or the HOMO level of the p-type host is lower than the HOMO level of the guest by 0.1 eV or more.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: March 27, 2018
    Assignee: Semiconducor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Nobuharu Ohsawa, Satoko Shitagaki, Hideko Inoue, Hiroshi Kadoma, Harue Osaka, Kunihiko Suzuki, Yasuhiko Takemura
  • Patent number: 9929373
    Abstract: A display device includes: a light emitting element including a light emitting layer and an anode and a cathode that hold the light emitting layer therebetween; and a sealing layer that seals the light emitting element. The sealing layer includes an organic layer and a first inorganic layer and a second inorganic layer that hold the organic layer from an upper side and a lower side. The organic layer is a cholesteric liquid crystal layer with a circularly polarizing function.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: March 27, 2018
    Assignee: Japan Display Inc.
    Inventor: Akinori Kamiya