Patents Examined by Terrell S Johnson
  • Patent number: 10361687
    Abstract: A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 23, 2019
    Assignee: FINISAR CORPORATION
    Inventors: Georgios Kalogerakis, The'linh Nguyen, Timothy G. Moran
  • Patent number: 10346179
    Abstract: An information processing apparatus having a function of entering and returning from a hibernation state and communicable with a server apparatus performing device certification includes a storage unit configured to, in a case where a software module is activated, store a hash value of the activated software module in a volatile memory, a request unit configured to request device certification based on a hash value stored in the volatile memory from the server apparatus, and an excluding unit configured to, in a case where the device certification is requested after returning from the hibernation state, exclude a software module activated before entering the hibernation state from a target of the device certification.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: July 9, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Kishi, Koji Harada, Junichi Hayashi, Nobuhiro Tagashira, Takami Eguchi, Yasuhiro Nakamoto, Ayuta Kawazu
  • Patent number: 10331456
    Abstract: A loading order according to which function modules are to be loaded from a storage unit is determined based on a predicted use situation of a user. The function modules are loaded according to the loading order thus determined. Subsequently, the function modules thus loaded are started up according to a start-up instruction. With such an arrangement, by determining the loading order based on a prediction of the user's desired function, such an arrangement enables a reduction in the length of a loading time that bothers the user.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: June 25, 2019
    Assignee: Janome Sewing Machine Co., Ltd.
    Inventors: Takeshi Kongo, Nobuhiko Kobayashi
  • Patent number: 10317966
    Abstract: A voltage regulation (VR) module of an Information Handling System (IHS) operates a switching direct current to direct current (DC-DC) voltage regulation (VR) power circuit in a constant current mode at a constant current level. The VR module approximates the capacitance value of the output capacitive load at the output terminal of the switching DC-DC VR power circuit based upon a time interval for output voltage to reach a threshold. The VR module then operates the switching DC-DC power circuit in constant output voltage mode using one group of VR operating settings to optimize performance for the capacitance value of the output capacitive load.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: June 11, 2019
    Assignee: Dell Products, L.P.
    Inventors: Ralph H. Johnson, Shiguo Luo
  • Patent number: 10310756
    Abstract: Embodiments of the application provide a node interconnection apparatus, a resource control node, and a server system. The node interconnection apparatus includes a computing node and a resource control node, and a device interconnection interface connecting the two. Each of the computing node and the resource control node comprises a processing unit and a memory, and the resource control node further comprises a resource interface for connecting with one or more storage devices. The resource control node manages storage resources of the storage devices, and when a storage resource is required by the computing node in performing a computing task, the resource control node allocates the storage resource in the storage devices for the computing node. The computing node can be powered off to save the energy, while the resource control node remains powered on, so that the access to the storage devices is not affected.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: June 4, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Baifeng Yu, Zhou Yu, Jiongjiong Gu
  • Patent number: 10310548
    Abstract: A circuit block is operated, for limited times, at a boosted frequency that is above the conventional maximum operating frequency specified to achieve an expected lifetime goal. The aging caused by both regular operation and boosted frequency operation is estimated and tracked block-by-block over the both the lifetime of the part and over shorter windows of time (e.g., daily, weekly, monthly, etc.) The shorter time windows are dynamically assigned aging budgets to ensure the part will still be expected to meet the expected lifetime even though its aging will be at an ‘accelerated’ rate whenever the block is operated at a boosted frequency. Aging budgets are assigned based on estimates of the amount of aging the block has experienced, and the amount of aging budget that is left for that time window.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: June 4, 2019
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Hee jun Park, Robert Allen Shearer, Victorya Vishnyakov
  • Patent number: 10295412
    Abstract: An integrated circuit counter includes a segmented thermometer coding counter architecture that reaches the thermodynamic energy minimum for a forward/reverse counting operation, requiring only one write or one erase operation per count so that energy consumption can be minimized, and circuit endurance maximized.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: May 21, 2019
    Assignee: AEROFLEX COLORADO SPRINGS INC.
    Inventors: David B. Kerwin, Alfio Zanchi
  • Patent number: 10296740
    Abstract: The invention relates to a system for protecting a computerized device from activities within the device bootstrap, which comprises: (a) a DC supply monitoring unit for monitoring power consumption of the DC supply of the device during bootstrap; and (b) a database for storing one or more valid bootstrap signatures, each of said valid bootstrap signatures describes a valid variation of power consumption pattern, respectively, from the DC supply of the device; wherein, during bootstrapping of the device, said DC supply monitoring unit continuously monitors the power consumption from said DC supply of the device, compares characteristics of the power consumption with said one or more valid bootstrap signatures in said database, and alerts upon detection of a mismatch.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: May 21, 2019
    Assignee: B.G. Negev Technologies and Application Ltd., at Ben-Gurion University
    Inventors: Mordechai Guri, Yuval Elovici
  • Patent number: 10283173
    Abstract: Methods and apparatuses for intelligently managing backup capacitors in a storage device. The power consumption of the device is monitored in order to determine a current backup energy requirement comprising an amount of energy needed to power the device for data-backup and power-down operations in the event of an interruption of main power to the device. Based on the current backup energy requirement, one or more of a plurality of backup capacitors of the device are turned on or off, wherein the plurality of backup capacitors are configured such that those of the plurality of backup capacitors remaining in the on state provide backup energy to the device during the interruption of main power.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: May 7, 2019
    Assignee: Seagate Technologies LLC
    Inventors: Sathish Narayanan, Vinayak Vithalkar, Eric Pius Pradeep
  • Patent number: 10275006
    Abstract: An information processing device includes a memory to store a power consumption amount for each first time interval output at each first time interval and an occurrence time of a first event which occurs during the first time interval, and a power estimation processor configured to calculate a power consumption amount in the event of an occurrence of the first event, on the basis of the power consumption amount for each first time interval output at each first time interval, and the occurrence time of the first event.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: April 30, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Miyuki Matsuo, Kohta Nakashima
  • Patent number: 10268255
    Abstract: A processor includes an execution engine and a power controller. The execution engine includes circuitry to determine an increased current for the execution engine. The power controller includes circuitry to determine a new dynamic capacitance for the execution engine based upon the increased current, calculate a new power consumption for the execution engine based upon the new dynamic capacitance, utilize the new power consumption to evaluate a new aggregate demand for power of a plurality of engines including the execution engine, and evaluate power provisioning of the processor based upon the new power consumption for the execution engine.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: Nir Rosenzweig, Efraim Rotem, Alexander Gendler, Ankush Varma
  • Patent number: 10268260
    Abstract: An ATX dual-output power supply unit with buck detection compensation ability has a voltage compensation unit connected to a first motherboard and a second motherboard. The power supply unit includes a circuit buck detection unit, a switch buck detection unit, a summarizing unit and a gain-lag comparison unit. The circuit buck detection unit serves to detect the circuit voltage loss between the first and second motherboards to output a circuit loss signal. The switch buck detection unit serves to detect the switch voltage loss between the power supply unit and the first and second motherboards to output a switch loss signal. The summarizing unit serves to summarize the circuit loss signal and the switch loss signal to generate a total buck loss signal. According to the total buck loss signal, the gain-lag comparison unit drives the voltage compensation unit to perform voltage compensation.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: April 23, 2019
    Assignee: Ryantek Co., Ltd.
    Inventor: Liang-Chun Lu
  • Patent number: 10234928
    Abstract: A display device includes interface circuitry configured to receive a display signal from an external computing device; a display screen configured to display the received display signal; an energy management function configured to control an operating state of the display device; a sensor configured to provide at least one control signal indicative of the presence of a user in a predefined area in front of the display screen; and a control unit configured to select an energy saving mode from a plurality of energy saving modes based at least on the control signal provided by the sensor.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: March 19, 2019
    Assignee: Fujitsu Technology Solutions Intellectual Property GmbH
    Inventor: Angel Chen
  • Patent number: 10235184
    Abstract: According to one embodiment, an active cable assembly may include a cable end, a data receiver, a controller characteristic circuit, and a controller. The data receiver, operable to receive a DC-balanced data signal, can be electrically coupled to a conductive input data line of the cable end. The controller characteristic circuit can be electrically coupled to the conductive input data line. The controller can be communicatively coupled to the data receiver. The controller may include a configurable communication port electrically coupled to the controller characteristic circuit, and memory for storing a boot loader. The controller can execute the boot loader to set the configurable communication port as an output for controller data signals and as an input for the controller data signals.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: March 19, 2019
    Assignee: Corning Optical Communications LLC
    Inventor: Richard Clayton Walker
  • Patent number: 10223412
    Abstract: Systems and methods for facilitating on-demand delivery and processing of program(s) and program-compatible application(s) on a plurality of different machines. In an embodiment, a metadata-driven command processor on a machine sends a request for a booting program and application to an agent. In response to the request, the agent invokes a resource to generate a booting program dataset that defines the booting program and an application dataset that defines the application, generates a response dataset comprising two or more nested datasets, wherein the two or more nested datasets comprise at least the booting program dataset and the application dataset, and sends the response dataset to the metadata-driven command processor. The metadata-driven command processor copies the booting program dataset and the application dataset into a process dataset comprising two or more nested datasets, and processes the first process dataset to execute the booting program and application on the machine.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: March 5, 2019
    Inventor: Douglas T. Migliori
  • Patent number: 10223017
    Abstract: A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: March 5, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen
  • Patent number: 10216218
    Abstract: An apparatus includes control circuitry configured to receive a first N-bit count value in a first domain, and to determine an M-bit increment indicating value based on the first N-bit count value and a reference value, where M<N. Boundary circuitry is configured to provide the M-bit increment indicating value to a second domain. In the second domain, updating circuitry configured to update a second N-bit count value based on an increment represented by the M-bit increment indicating value provided by the boundary circuitry.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: February 26, 2019
    Assignee: ARM Limited
    Inventor: Alex James Waugh
  • Patent number: 10216250
    Abstract: A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access to the non-volatile memory units. In a normal mode and during a period of accessing the non-volatile memory units by the control chip, if the non-volatile memory units are in a busy state, the energy-saving control unit controls the clock generation unit to stop outputting an internal clock signal to the specific circuit group, so as to reduce power consumption of the control chip.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 26, 2019
    Assignee: VIA Technologies, Inc.
    Inventors: Yi-Lin Lai, Chen-Te Chen
  • Patent number: 10209761
    Abstract: Various embodiments of the present technology may comprise a method and apparatus for a power management unit. The power management unit may be configured to operate in conjunction other integrated circuits to mitigate power dissipation. The power management unit may receive temperature information from a temperature sensor and deploy various power management schemes to reduce the leakage power of an SRAM. The power management schemes may be based on the particular characteristics of the SRAM.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: February 19, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Dannie Gerrit Feekes, Jr.
  • Patent number: 10203962
    Abstract: A TigerSharc DSP boot management chip and the method thereof, the boot management chip comprises an interface unit, a two-port RAM unit, a management unit and a DSP download management unit; further comprises a flash drive unit and a NOR flash chip; the management unit is connected to the flash drive unit; the two-port RAM unit is connected to the NOR flash chip via the flash drive unit; and, the NOR flash chip is communicated with the DSP download management unit via the flash drive unit. The management unit provides two booting modes: booting via the NOR flash chip or booting via an external bus; the host boot startup method is improved and two booting program download methods are provides, which can greatly improve the booting speed of the TigerSharc DSP chip.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: February 12, 2019
    Assignee: CRRC QINGDAO SIFANG ROLLING STOCK RESEARCH INSTITUTE CO., LTD.
    Inventors: Zhen Li, Guobin Sun, Xiaosong Zhang