Abstract: An electronic device includes: a memory device; a nonvolatile memory configured to store a plurality of first configuration parameters respectively corresponding to operating voltages of the memory device and a plurality of second configuration parameters respectively corresponding to operating temperatures of the memory device; and a memory controller configured to: determine a value of a third configuration parameter corresponding to an operating voltage of the memory device among the plurality of first configuration parameters stored in the nonvolatile memory without performing a training operation, determine a value of a fourth configuration parameter corresponding to an operating temperature of the memory device among the plurality of second configuration parameters stored in the nonvolatile memory without performing the training operation, and drive the memory device according to the determined values of the third and the fourth configuration parameters.

Abstract: A power supply combination comprises two multi-voltage power sources having respective power rails delivering power at a first voltage and respective power rails delivering power at a second voltage. The power supply combination also comprises two single-voltage power sources having respective power rails delivering power at the first voltage. A first power combining circuit is electrically connected to the first voltage power rails of two multi-voltage power sources and to the two single-voltage power sources and delivers power at the first voltage to a first voltage input of a load. A second power combining circuit is electrically connected to the second voltage power rails of the two multi-voltage power sources and delivers power at the second voltage to a second voltage input of the load. A power supply network may connect a plurality of power supply combinations to a power management unit for reporting failures of the power sources.

Abstract: A spare capacity status of each of multiple computing systems in a data center is monitored. Temporary workloads are assigned to these computing systems if there exists sufficient additional electrical power supply and capacity on power distribution lines. Thus, computing systems that are typically not productively used, such as those that are about to be decommissioned, have not yet been assigned for normal servicing, are reserved for special circumstances, or that are assigned to services that are currently in low demand, are temporarily used for productive data center purposes.

Abstract: An apparatus includes an execute circuit configured to execute a plurality of operations received from a queue, as well as a power estimator circuit, and a power sensing circuit. The power estimator circuit is configured to predict power consumption due to execution of a particular operation of the plurality of operations, and to withdraw, based on the predicted power consumption, a first amount of power credits from a power credit pool. The power sensing circuit is configured to monitor one or more characteristics of a power supply node coupled to the execute circuit to generate a power value, and to deposit a second amount of power credits into the power credit pool. The second amount of power credits may be based on the power value indicating that power consumed during the execution of the particular operation is less than the predicted power consumption.

Abstract: The present disclosure relates to a power circuit including a power supply circuit and a first control circuit. The power supply circuit is electrically connected to a power supply source and a power terminal for selectively providing power to the power terminal. The first control circuit is electrically connected to the power supply circuit and configured to receive a detection signal to enable or disable the power supply circuit. When the detection signal is enabled, the first control circuit provides a first enable signal to the power supply circuit, so that the power supply circuit provides power to the power terminal. When the detection signal is at the disable level, the first control circuit is configured to provide the first disable signal to the power supply circuit, so that the power supply circuit stops providing power from the power supply source to the power terminal.

Abstract: A leakage protection circuit can include: a pull-down current generation circuit coupled between output terminals of a rectifier circuit; and a control circuit configured to control the pull-down current generation circuit to generate a pull-down current during a predetermined time interval, and to determine whether leakage occurs in accordance with a voltage detection signal that is representative of an output voltage of the rectifier circuit.

Abstract: A logic circuitry package for a replaceable print apparatus component includes an interface including a power terminal and at least one logic circuit. The at least one logic circuit is configured to respond to communications sent to a first address via the interface and respond to communications sent to a second address via the interface. The at least one logic circuit is configured to in response to a first command sent to the first address, draw a first current on the power terminal; and in response to a hibernate command sent to the first address, respond to communications sent to the second address and draw a second current on the power terminal less than the first current.

Abstract: The present application is applicable to the field of integrated circuit technology, and provides a data writing method, system, apparatus, device and medium for an integrated circuit chip. The data writing method is applied to a writer, the integrated circuit chip is electrically connected with the writer through a power-supply positive terminal and a power-supply negative terminal, and the data writing method includes: sending a data writing order to the integrated circuit chip, where the data writing order is configured to instruct the integrated circuit chip to enter a data writing mode after receiving the data writing order; and performing data writing to the integrated circuit chip by controlling an electrical parameter of an input voltage of the power-supply positive terminal or the power-supply negative terminal of the integrated circuit chip after the integrated circuit chip enters the data writing mode.

Abstract: Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.

Abstract: A power supply device includes a combination of one power supply module of a plurality of power supply modules having different power supply performances and one controller of a plurality of controllers having different functions, which are selectively combined. Each of the plurality of power supply modules includes a power supply module side connection portion common to the plurality of power supply modules, and each of the plurality of controllers includes a controller side connection portion common to the plurality of controllers and connectable to the power supply module side connection portion, to allow the one power supply module and the one controller are selectively combined.

Abstract: For selectively providing notifications based on charge history, methods, apparatus, and systems are disclosed. One apparatus includes a processor and a memory that stores code executable by the processor. The processor determines a device location for the apparatus and identifies a charge history corresponding to the device location. The processor further selects a notification based on the charge history and presents the notification based on a charging status of the apparatus.

Abstract: One aspect of the present disclosure involves dynamically performing power capping with respect to a group of computing systems. Different priority levels can be assigned to at least some of the individual computing systems within the group of computing systems. Individual power limits can be set for the plurality of individual computing systems based at least in part on the different priority levels and utilization levels of the plurality of individual computing systems. Another aspect of the present disclosure involves dynamically performing power capping with respect to various subsystems of a computing system. Different priority levels can be assigned to at least some of the plurality of individual subsystems within the computing system. Individual power limits can be set for the plurality of individual subsystems based at least in part on the different priority levels and current power consumption of the plurality of individual subsystems.

Abstract: Maintaining a smart contact lens power level by receiving smart contact lens power level data, determining a smart contact lens power level need according to the power level data, and instigating relative motion between a smart contact lens induction coil and a static magnetic field to meet the smart contact lens power level need.

Abstract: A storage system includes a redundancy group formed of storage drives that stores host data and redundant data in a distributed manner, and a controller that controls access to the redundancy group. The controller is configured to: select, from among the storage drives in the redundancy group, a part of the storage drives in an upper limit number equal to or smaller than a redundancy level of the redundancy group, and set the part of the storage drives to a power saving state; receive, from a host, a read request with respect to a target storage drive in the redundancy group; and restore, when the target storage drive is in the power saving state, target data corresponding to the read request from data collected from a part of the storage drives different from the target storage drive in the redundancy group, and return the target data to the host.

Abstract: A system includes a plurality of items of master equipment, each having a programing interface, and a plurality of slave equipment. An interconnect circuit is coupled between the items of master equipment and the items of slave equipment. Each transaction is assigned an attribute capable of taking on at least two attribute values corresponding to at least two states for the master equipment. Each item of slave equipment is associated with an identifier capable of taking on at least two values corresponding respectively to at least two properties for the slave equipment. Each item of master equipment automatically inherits the property of its programing interface. A filtering circuit is configured to, in the presence of a transaction intended for an item of slave equipment, compare the corresponding attribute value with an identifier value of the intended slave equipment and reject or not reject the transaction based on the comparison.

Abstract: A circuit board incorporable into an apparatus includes a substrate, a reception unit that is provided on the substrate and that wirelessly receives a function program for achieving a function, a storage unit that is provided on the substrate and to which a writing program for writing the function program received by the reception unit has been written in advance, a power supply provided on the substrate, and a power control unit that supplies power for receiving, with the reception unit, the function program and power for writing, on a basis of the writing program, the function program to the storage unit using the power supply without using an external power supply.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to monitor and manage usage of resources on a computing platform. An example apparatus includes a processor and a subsystem. The example processor includes a modified operating system, the operating system modified to monitor application execution via the processor to determine a usage scenario for the apparatus. The example processor includes an index generator to generate a system usage scenario index quantifying a snapshot of the usage scenario for the processor and the subsystem of the apparatus. The example processor includes a rebalancer to reallocate resources of at least one of the processor or the subsystem based on the system usage scenario index.

Abstract: A circuit breaker includes an electromechanical switch, a current sensor, a voltage sensor, and a processor. The electromechanical switch is serially connected between a line input terminal and a load output terminal of the circuit breaker, and configured to be placed in a switched-closed state or a switched-open state. The current sensor is configured to sense a magnitude of current flowing in a path between the line input and load output terminals and generate a current sense signal. The voltage sensor is configured to sense a magnitude of voltage at a point on the path between the line input and load output terminals and generate a voltage sense signal. The processor is configured to receive and process the current sense signal and the voltage sense signal to determine operational status information of the circuit breaker and determine power usage information of a load connected to the load output terminal.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

Abstract: In some examples, after a jack of a power supply is connected to a port of a device, a first safety chip may provide a signal that includes an amount of power sufficient to power a second safety chip located in the power supply. After receiving a message from the second safety chip, the first safety chip may send the second chip an instruction to cause relays in the power supply to transition from open to closed, causing power to be provided by the jack to the computing device. The first safety chip may repeatedly send a continue instruction requesting the second chip to keep the relays in the closed position. If the jack is disconnected from the port, the second safety chip fails to receive the continue instruction and causes the relays to transition back to the open position, stopping power from being provided by the power jack.