Abstract: Serial port circuitry (2) for use in a mass data storage device (5) and a method for configuring and operating it are disclosed. The serial port circuitry includes a serial port (2) for providing information from circuitry within the mass data storage device (5) for use external to said mass data storage device and user programmable circuitry connected to the serial port to receive externally applied signals (6) to modify at least one parameter of said mass data storage device (5). The user programmable circuitry preferably includes a sequencer (12, 18, 22) programmed to selectively provide at least two different serial port control outputs (162,212) to modify at least two parameters of said mass data storage device. The sequencer (12, 18, 22) executes pre-established program instructions contained in a RAM (12) to control the mass data storage device.

Abstract: A high-speed clock-synchronous memory device is provided with a sense amplifier S/A shared by and between cell arrays, and a cell array controller unit CNTRLi, wherein input and output of data/command synchronous with the clock, access command supplies all address data bits (row and column) simultaneously. By acknowledging a change in bits observed between two successive commands, regarding some of address bits configuring access address, the device judges whether the current access is made within the same cell array as the preceding access, between the neighboring cell arrays, or between remote cell arrays. According to the judgement, suitable command cycle is applied. At this time, the command cycle satisfies relationship: S≧N≧F.

Abstract: A method is used to fully extract coupling coefficients of a flash memory cell by a GIDL manner. The flash memory cell is composed of a substrate, a drain region, source region, a control gate and a floating gate. The method keeps the source voltage Vs and the substrate voltage Vb fixed. The drain voltage Vd and the control gate voltage are varied. Then, measuring a GIDL current obtains a first coefficient ratio of the drain coupling coefficient ad to the gate coupling &agr;cg, that is, &agr;d/&agr;cg. Similarly, keeping the drain voltage Vd and the substrate voltage Vb fixed and varying the source voltage Vs and the control gate voltage Vcg, a second coefficient ratio of the source coupling coefficient &agr;s to the gate coupling coefficient &agr;cg, that is, &agr;s/&agr;cg.

Abstract: A ferroelectric random access memory including a plurality of bit lines extending in one direction, a plurality of word lines extending in another direction perpendicular to the one direction, and a plurality of unit cells arranged in an M×N array while being connected to associated ones of the lines. The unit cells are grouped into a plurality of unit cell groups. A dummy cell group comprises a plurality of dummy cells that are connected to an associated one of the bit lines of an optional position on the associated bit line.

Abstract: There is disclosed a method of erasing a flash memory device. The present invention implements a dummy recovery operation after a recovery operation for recovering the threshold voltage of an over-erased memory cell is implemented. Therefore, it can reduce the flow of the leakage current through bit lines to thus improve the program characteristic of the device.

Abstract: Integrated circuit memory devices are tested by loading into a first defect interpretation memory, results of a preceding comparison test between test pattern data that is input into a memory device and resultant data that is output from the memory device. Automatic switching then takes place to a second defect interpretation memory. The results of a succeeding comparison test are loaded therein, while simultaneously analyzing results from the preceding comparison test in the first defect interpretation memory. Then, automatic switching back to the first defect interpretation memory takes place, and results of a next succeeding comparison test are loaded therein while simultaneously analyzing the results from the succeeding comparison test in the second defect interpretation memory. Automatic switching and automatic switching back are repeatedly performed, to thereby simultaneously test a memory device and analyze memory test results.

Abstract: A semiconductor device according to the present invention includes a plurality of test mode circuits. Each test mode circuit includes a plurality of decode circuits decoding an input signal and a plurality of latch circuits. Each decode circuit generates a test mode signal. The test mode signals are held in the latch circuits. Each test mode circuit further includes decode circuits outputting a group reset signal for resetting a corresponding latch circuit. Thus, a plurality of test mode signals can be combined arbitrarily and serially.

Abstract: A nonvolatile semiconductor memory device includes a program state detection circuit for checking a state of programmed memory cells. The program state detection circuit checks program pass/fail using data transmitted through a column selection circuit, according to a column address having redundancy information. Therefore, it is possible to overcome the problem that the memory device is regarded as a fail device owing to a defective column.

Abstract: A device for storing pixel information for displaying a graphics image on a display includes a frame buffer and a processor. The information includes an intensity value and a value associated with each of a plurality of additional planes for each pixel. The frame buffer memory has a series of consecutive addresses for storing information to be output to the display. The frame buffer may be subdivided into a plurality of blocks, where each block corresponds to a region of the display having a plurality of contiguous pixels. The processor places the pixel information within the frame buffer memory so that in a given block there are placed at a first collection of consecutive addresses the intensity values for each of the pixels in the block.

Abstract: An apparatus, program product, and method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) introduce switching history effects to a memory cell under test to stress the memory cell such that a reliable determination of stability may be made. It has been found that the worst case scenario for memory cell stability typically occurs immediately after a memory cell is switched to one state after the memory cell has been maintained in the other, opposite state for a period of time sufficient to introduce switching history effects. As such, a testing process may be configured to maintain a memory cell in a particular state for a period of time sufficient to introduce switching history effects, whereby the memory cell may be adequately stressed during the testing process to highlight any stability problems by setting the memory cell to an opposite state, and then shortly thereafter disturbing the memory cell, e.g.

Abstract: In a EEPROM memory architecture organized into word columns that includes n memory cells per word column, there is, for each word of the column, one diffusion line to connect sources of the memory cells to a ground connection transistor using a source line. A word read access includes simultaneously selecting the word accessed in a read mode in a first group of memory cells, and an additional word in the second group of memory cells. Each column has n bit lines ranked 0 to n−1, each connected to the same ranked cells in the first group of memory cells.

Abstract: A semiconductor memory device is provided for simultaneously reading data of a plurality of bits from its memory cell region and outputting the data successively to an external environment, and includes: an external output section whose output state to the external environment is altered for one output logical level and not altered for another output logical level; a output level generation section for assigning a logical level corresponding to the content of bit-data to a bit freely selected out of the data, and assigning another output logical level to another bit; and a supply section for successively supplying the output logical levels, generated by the output level generation section to correspond with respective bits of the data, to the external output section.

Abstract: A semiconductor memory device, such as a SDRAM, includes input/output data line pairs, data bus line pairs, and a redundancy data bus line pair. The input/output data line pairs are connected to a corresponding one of the data bus line pairs and an adjacent one of the data bus line pairs via redundancy shift switches, with a last one of the input/output data line pairs being connected to a last one fo the data bus line pairs and the redundancy data bus line pair. Sense buffers and write amplifiers are connected between each of the data bus line pairs and the redundancy data line pair. The shift switches are located closer to the input/output data line pairs than the sense buffers and the write amplifiers so that data read from the memory cells is less effected by the on resistance and the parasitic capacitance of the switches. When the switches are located closer to the data bus lines than the sense buffers and the write amplifiers are, the switches effect the data signals of data read from the memory cells.

Abstract: A power conservation system which provides for fast and efficient transitions between fast and slow processor clocking speeds. The slow processor clocking speed minimizes power consumption during periods of processor inactivity (idle states) or low priority execution. The fast processor clocking speeds are utilized during periods of processor activity (active states) or high priority execution. Used in conjunction with a context-sensitive processor, the power conservation system is able to monitor the state of the processor and modify the processor clocking speed accordingly.

Abstract: An electronic control unit is provided with a microcomputer, a power supply circuit and a filter circuit. The microcomputer comprises a CPU, a ROM, a RAM and a SRAM. A voltage-drop detecting circuit within the power supply circuit receives a constant voltage generated in a constant voltage circuit and outputs a voltage detection signal WI by monitoring fall of such constant voltage. The filter circuit also receives the WI signal, generates a WI(A) signal and a WI(B) signal and outputs the WI(B) signal to the SRAM as the signal for restricting the data write operation. The CPU allows start of the data write operation to the SRAM and executes the write operation of data for each data that requires the concurrency when both WI(A) and WI(B) signals indicate permission of the data write operation.

Abstract: A static random access memory (SRAM) circuit includes four-transistor memory cells and is capable of high-speed reliable read operations. According to one embodiment, a SRAM circuit includes “n” memory cells (200-1 to 200-n) connected to digit line pairs (202-0 and 202-1). When selected, a memory cell (200-1 to 200-n) can draw an on current (Ion). When deselected, a memory cell (200-1 to 200-n) can draw a leakage current (Ioff) that can maintain a data value stored in a memory cell. High-speed and reliable operations may be achieved by meeting the following relationship: Ion>K*(n−1)*Ioff, where K is 1 or more.

Abstract: A synchronous semiconductor memory device performs input/output of data in synchronization with an externally applied external clock signal or a data strobe signal in a test operation mode. An operation of an internal circuit in the test operation mode is performed in synchronization with a dock signal produced by an internal control clock producing circuit and being faster than the external clock. In the test operation mode, a decode circuit produces write data based on data applied to a specific terminal among data I/O terminals, and a result of comparison of a plurality of read data is issued to the specific terminal during a data read operation.

Abstract: A magnetic switching device, includes a first electrode, a second electrode, and a nanoparticle having a magnetic moment and being disposed between the first and second electrodes. At least one of the first electrode and the second electrode includes a magnetic material which has a net spin polarization in its conduction band for injecting, into the nanoparticle, an electrical current including a net spin polarization for overcoming the magnetic moment of the nanoparticle upon selection of a predetermined magnitude for the electrical current.

Abstract: A semiconductor integrated circuit comprising memory cells and a holding unit. The holding unit holds write data to the memory cell and mask information for masking a predetermined bit or bits of the write data, both supplied corresponding to a write command, as held write data and held mask information. On receiving a next write command, the semiconductor integrated circuit masks held write data in accordance with held mask information and writes the resultant to the memory cell. The holding unit holds next write data and next mask information supplied corresponding to this write command as held write data and held mask information. That is, the held write data and the held mask information are rewritten. Thereby, the semiconductor integrated circuit which writes write data previously accepted upon the reception of a next write command can mask the write data.

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.