Abstract: A method of measuring a delay time in a semiconductor device which has a particular circuit subject to delay time measurement, a test circuit coupled to an input terminal of the particular circuit for bypassing the particular circuit, and a selector for selectively outputting either an output signal from the particular circuit or an output signal from the test circuit.

Abstract: A method and circuit for preventing forward bias of a collector-substrate diode in an integrated circuit with a bipolar transistor where a load driven by the transistor may be offset from a reference voltage, such as circuit ground, by a varying voltage offset. The difference between the bipolar transistor collector voltage and the reference voltage is sensed, and the bipolar transistor base current is varied responsive to the sensed difference so that the base current is zero when the collector voltage is equal to the reference voltage, whereby the collector current will be less than .beta. times the base current when the emitter voltage is less than the reference voltage and the diode will not become forward biased.

Abstract: A substrate voltage supply control circuit for a memory which is capable of controlling substrate voltages having different voltage levels generated from a substrate voltage generating circuit included in the memory, so that different substrate voltages may be supplied to each circuit in memory depending on the state of each circuit, thereby reducing electrical power consumption in memory.

Abstract: A high side monolithic switching circuit integrated into a silicon chip is described in which the charge pump is connected to the ground terminal by a constant current circuit and floats relative to the ground terminal to reduce noise generation. The charge pump is connected to a V.sub.cc terminal by an auxiliary power MOSFET having its gate connected to the charge pump output circuit. The conventional charge pump diodes are implemented as MOSFET devices which can be easily integrated into the common monolithic chip. A clamping circuit across the charge pump permits the use of a low voltage, small area capacitor for a high voltage device.

Abstract: A substrate potential detection circuit includes a substrate potential detection unit including a first transistor having a gate and a source connected respectively to a ground line and a reference voltage line, a second transistor having a gate receiving a substrate potential and a drain connected to the ground, and a third transistor having a source connected to the drain of the first transistor and a gate and a drain connected in common to the source of the second transistor to form a detection output node; and a buffer circuit having a drive transistor and a current source, a gate and a source of the drive transistor being connected respectively to the detection output node and the reference voltage line and outputting a substrate detection voltage.

Abstract: An integrated circuit configuration for generating a reference current by bipolar technology includes a transistor of one conduction type having a control terminal being acted upon by a reference voltage and having a load path. An externally connectable resistor is to be connected between the load path of the transistor and a reference potential. A current mirror configuration has an input side connected between the load path of the transistor and a supply voltage source and has an output for picking up a reference current.

Abstract: An electronic clamping circuit is provided in one preferred embodiment, the clamping circuit includes a pair of series-connected diodes, both having the same bias, which are shunted across a feedback path of a transimpedance amplifier circuit. A capacitive element is connected to a node in-between the diodes and a potential (e.g., ground). The arrangement of the diodes and capacitive element serve to keep the amplifier circuit's operation within its linear limits without severely degrading its bandwidth.

Abstract: A protection circuit inhibits saturation and damage of sensitive circuit elements when an input signal goes out of a nominal input range. The protection circuit includes an out-of-range detector which compares the input signal to reference levels to determine if it is within the range. If it is not, a control circuit substitutes a supplemental signal that is slightly out of range, but not so far out of range as to cause any substantial saturation. Supplemental signal sources that produce supplemental signals slightly outside the high and low ends of the range with error margins, not more than about 750 mV, that lie just outside the range; an out-of-range input is replaced by the supplemental signal with the closest value. The invention is particularly applicable to multistep/subranging analog-to-digital/converters.

Abstract: A biasing system for a differential amplifier includes an NMOS current source and a gate bias voltage generator. The gate bias voltage generator produces a bias voltage VNCS to control the NMOS current source. The gate bias generator includes a reference current generator to produce a reference current relatively independent of supply voltage variations. A temperature compensator regulates the reference current to provide a temperature compensated current. A current mirror duplicates the temperature compensated current to a bias voltage generator. The bias voltage generator generates the bias voltage.

Abstract: An object of the present invention is to provide a power line connection circuit which obtains a desired turn-on resistance and a turn-off resistance without using a complex external circuit. The power line connection circuit provides a MOS transistor arranged in a power supply line, whose continuity is changed by applying a control signal from a control unit; a voltage conversion means for converting the voltage of the control signal; and a clamp means for clamping the converted voltage output from the voltage conversion means so as to have a predetermined voltage difference with respect to the voltage of said power supply line.

Abstract: Embodiments of the present invention bias a field effect transistor with only a single voltage source and generally do not have the disadvantages of traditional "floated source" bias techniques. Furthermore, some embodiments of the present invention are capable of automatically compensating for the normal manufacturing variations that often result in the physical characteristics of individual FETs.

Abstract: A system for controlling the application of power by a power supply to a load. The inventive system includes a first circuit for drawing power from the power supply and a second circuit for controlling the amount of power drawn by the first circuit from the power supply. The amount of power drawn from the power supply is gradually increased prior to the application of power to the load and gradually decreased after removal of power from the load. In the illustrative embodiment, the first circuit is a digitally controlled resistance and the second circuit is a digital counter which supplies a control word for the digitally controlled resistance. A high order bit from the counter enables the gating of clock pulses to the load circuit. As a result, activation of the load circuit is delayed while the invention gradually varies the amount of power drawn from the power supply to a desired threshold level.

Abstract: A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages. The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock. Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages. Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge. The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal. Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode. In a method of use, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value.

Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.

Abstract: A control system for controlling periodic disturbances employing a delayed inverse filter (5), a variable delay (6), a controller, a system model (4) and a comb filter (9).

Abstract: A digitally controlled oscillator in a digital phase-locked loop provides an additional output signal which indicates the time difference between clock pulses output from the digitally controlled oscillator and clock pulses of an ideal clock signal of the same average frequency. This additional signal is called a residue signal. This residue signal may then be used to extrapolate or interpolate outputs of continuously variable interpolation or decimation filters using the output clock signal of the digital phase-locked loop generated according to the digitally controlled oscillator. Because the residue signal may be used in interpolation or decimation filters, it is also applicable to analog-to-digital converters, digital-to-analog converters and sample rate converters which use such filters. The digital phase-locked loop circuit is simpler than previous circuits because a conventional overflowing accumulator may be used, which is a first order system, rather than a higher order multi-bit noise shaper.

Abstract: A monolithic microwave semiconductor integrated circuit including a bias stabilizing circuit of a current mirror type formed of a bias control transistor formed of an enhancement mode compound semiconductor field effect transistor and a biased transistor formed of an enhancement mode compound semiconductor field effect transistor.

Abstract: A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provided by a plurality of delay elements. A first particular number of the binary signals of greatest binary significance are decoded to provide, in a thermometer code, a plurality of signals each having first and second amplitudes. The signals in the thermometer code control the operation of individual switches each having first and second operative relationships to provide respectively for a maximum delay or a minimum delay in an associated one of the delay elements. The binary signals of least binary significance are decoded to produce an analog signal variable between the first and second amplitudes.

Abstract: A constant current generating circuit is provided with a first current generating circuit unit which generates a first current having a positive temperature dependency and includes a pair of first and second bipolar transistors, a first current mirror circuit comprised of a plurality of first MOS transistors which regulates a current density ratio of the currents fed to the first and second bipolar transistors to be constant and derives the first current and a first circuit disposed between the first and second bipolar transistors and the first current mirror circuit for limiting dependency of the currents flowing through the first and second bipolar transistors on a voltage of a power source applied to the first current mirror circuit, a second current generating circuit unit is also provided which generates a second current having as negative temperature dependency and which includes a third bipolar transistor and a second resistor through which the second current is derived.

Abstract: A pulse signal generator includes a first delay device for delaying an input pulse signal and converting the input signal into a first intermediate signal. A power supply voltage detector detects a power supply voltage and outputs a signal representative thereof. A second delay device serves to delay the first intermediate signal and to convert the first intermediate signal into a second intermediate signal in response to the output signal from the power supply voltage detector. A logic OR operation is executed between the first and second intermediate signals, and an output signal is generated in response to the first and second intermediate signals. The output signal has a pulse width, which is greater than a pulse width of the input signal when the power supply voltage lies in a predetermined range.