Abstract: Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time.

Abstract: A voltage tolerant input/output circuit coupled to an input/output pad, and is able to support a voltage overdrive operation of approximately twice an operational voltage, and have an input tolerance of approximately three times the operational voltage. The circuit includes a pull-up driver, a P-shield, an N-shield, a pull-down driver and a cross-control circuit. The pull-up driver is coupled to a power supply. The P-shield has an N-well and is coupled to the pull-up driver at a node C, and coupled to the input/output pad. An N-shield is also coupled to the input/output pad. A pull-down driver is coupled between ground and the N-shield at a node A. A cross-control circuit is configured to detect voltages at: the node A, the node C, and the input/output pad. The cross-control circuit is configured to output control signals to the P-shield and the N-shield based on the detected voltages.

Abstract: A high voltage charge-pump includes a plurality of voltage boosting stages, a low voltage input, and at least one clock input. A sensing charge-pump having a voltage detector output has at least one voltage sensing stage that is communicably coupled to at least one of the plurality of voltage boosting stages. A loop filter in a feedback control loop includes a voltage detector input coupled to the voltage detector output, a voltage reference input, and a voltage error output. A voltage controlled oscillator (VCO) with a variable frequency output has a voltage error input coupled to the voltage error output. The feedback control loop also includes at least one driver having a variable frequency input coupled to the variable frequency output and at least one clock output coupled to the at least one clock input.

Abstract: An electric device and a control method of the same, the electric device including a load terminal, a constant voltage output unit to generate an output voltage to the load terminal, a feedback circuit having a plurality of feedback circuit elements to generate a feedback signal to the constant voltage output unit to adjust the output voltage, and a controller to set a power mode of the electric device and to generate a control signal according to an enable signal and the set power mode such that the control signal corresponds to one or more of the feedback circuit elements to adjust the feedback signal, wherein the enable signal corresponds to a level of the output voltage.

Abstract: A signal-noise ratio control system which reduces noise interference includes a touch sensor, a touch controller, and a level shifter. The touch sensor is driven by a driving signal and outputs an analog signal based on a touch situation. The touch controller generates the driving signal and provides a divided voltage based on the analog signal. The level shifter adjusts a voltage level of the driving signal based on a voltage level of the divided voltage.

Abstract: A polar modulator for generating a polar-modulated signal based on amplitude information and phase information includes a phase-locked loop which is implemented to enable a setting of a frequency depending on a control value to obtain a phase-locked loop output signal. The polar modulator further includes a modulation means which is implemented to combine an amplitude modulation signal derived from the amplitude information with the phase-locked loop output signal to generate the polar-modulated signal. The polar modulator further includes a control value generator which is implemented to high-pass filter an amplitude signal derived from the amplitude information, to obtain a high-pass filtered amplitude signal, wherein the control value generator is implemented to combine the high-pass filtered amplitude signal with a phase signal based on the phase information to generate the control value signal representing the control value.

Abstract: A system and method for charging heavy capacitive loads may comprise an n-stage stacked charging circuit wherein n is an integer greater than one which may comprise n?1 capacitors and a voltage supply, each sequentially electrically connected to the capacitive load in an order through a respective first through nth switch during a respective first through nth charging time period; the n?1th capacitors each sequentially electrically connected to the capacitive load in reverse order during a first through n?1th discharging time period through the respective n?1th through first switches. The system and method may comprise an n+1th switch electrically connecting the capacitive load to ground during an nth discharging period. The capacitive load may comprise a piezoelectric element, which may comprise an inkjet printer head inkjet actuator.

Abstract: A wireless transceiver includes an antenna array that transmits an outbound RF signal containing outbound data to remote transceivers and that receives an inbound RF signal containing inbound data from the remote RF transceivers, wherein the antenna array is configurable based on a control signal. An antenna configuration controller generates the control signal to configure the antenna array to hop among a plurality of radiation patterns based on a hopping sequence. An RF transceiver section generates the outbound RF signal based on the outbound data and that generates the inbound data based on the inbound RF signal. In one configuration, a switching section selectively couples a selected one of the antennas in the array to the RF transceiver section, based on the control signal. In another configuration, the RF transceiver section includes an RF section for each antenna in the array.

Abstract: A method for detecting an attack in an electronic microcircuit comprises: forming the microcircuit in a substrate, forming in the substrate a first well electrically isolated from the substrate, by a second well and an embedded well, forming in the first and second wells a data processing circuit comprising a ground terminal formed in the first well and a power supply terminal formed in the second well, and activating a detection signal when a voltage at the ground or power supply terminal of the data processing circuit crosses a threshold voltage.

Abstract: A substrate bias control circuit includes a process voltage temperature (PVT) effect transducer that responds to a PVT effect. A PVT effect quantifier is coupled to the PVT effect transducer. The PVT effect quantifier quantifies the PVT effect to provide an output. The PVT effect quantifier includes at least one counter and a period generator. The period generator provides a time period for the counter. A bias controller that is coupled to PVT effect quantifier is configured to receive the output of the PVT effect quantifier. The bias controller is configured to provide a bias voltage. The bias controller includes a bias voltage comparator.

Abstract: Embodiments of the present invention may provide a power supply system that uses a capacitive voltage divider to selectively monitor various power supplies on an IC chip. The power supply system may sample a monitored power supply to a capacitor and select certain capacitors from a set of switched capacitors to divide down the sampled voltage. The resulting voltage may be compared to a voltage reference. Using different selections of switched capacitors, the monitored power supply may be compared for different voltage levels. The ratio of the sampling capacitor to the selected capacitors may determine a voltage level the comparator will trigger. Further, based on the monitored power supply level, the power supply system may turn on a switch between an external power supply and a regulated digital power supply to charge the regulated digital power supply while a main LDO is turned off.

Abstract: A semiconductor device includes: a first field-effect transistor (FET); and a second FET of similar polarity to the first FET, wherein a body of the first FET is electrically coupled to a body of the second FET, and a source of the first FET is electrically coupled to a source of the second FET, such that a body voltage of the second FET controls a body voltage of the first FET.

Abstract: A temperature compensation circuit may include a temperature coefficient generator configured to generate a first signal and a second signal, wherein the first signal is proportional-to-absolute-temperature (ptat) and the second signal in negatively-proportional-to-absolute temperature (ntat), a first programmable element configured to multiply at a first programmable ratio an amplitude of a third signal having a negative temperature coefficient from a first temperature to a second temperature, and a second programmable element configured to multiply at a second programmable ratio an amplitude of a fourth signal having a positive temperature coefficient from the second temperature to a third temperature.

Abstract: A system for uniform power regulation of an integrated circuit is disclosed. In each of a plurality of regions, the system includes a comparison circuit having a first input coupled to receive a reference voltage and a second input coupled to receive a feedback voltage. The comparison circuit provides a gating voltage to a driver circuit that is coupled to a first supply voltage. The driver circuit is configured to provide a regulated voltage responsive to the gating voltage. A feedback adjustment circuit is configured to trim the regulated voltage by a region-specific trim value and output the trimmed regulated voltage as the feedback voltage on the output.

Abstract: In one implementation, an apparatus may include a first negative channel metal oxide semiconductor (NMOS) transistor circuit coupled to a first voltage source, a second NMOS transistor circuit coupled to the first voltage source, the second NMOS transistor circuit having a smaller channel width to channel length ratio than the first NMOS transistor circuit, a first positive channel metal oxide semiconductor (PMOS) transistor circuit coupled to a second voltage source and coupled to the second NMOS transistor circuit, and a second PMOS transistor circuit coupled to the second voltage source, the second PMOS transistor circuit having a larger channel width to channel length ratio than the first PMOS transistor circuit.

Abstract: Some embodiments of the present disclosure relate to regulators for charge pumps. Such regulators selectively activate a charge pump based not only on the voltage output of the charge pump, but also on an series of wake-up pulses that are delivered at predetermined time intervals and which are delivered independently of the voltage output of the charge pump. Hence, these wake-up pulses prevent extended periods of time in which the charge pump is inactive, thereby helping to prevent latch-up in some situations.

Abstract: Back-gate voltage control provides a high speed and low power consumption LSI operable in a wide temperature range in which a MOS transistor having back gates is used specifically according to operating characteristics of a circuit. In the LSI, an FD-SOI structure having an embedded oxide film layer is used and a lower semiconductor region of the embedded oxide film layer is used as a back gate. A voltage for back gates in logic circuits having a small load in logic circuit block is controlled in response to activation of the block from outside of the block. Transistors, in which the gate and the back gate are connected to each other, are used for the circuit generating the back gate driving signal, and logic circuits having a heavy load such as circuit block output section, and the back gates are directly controlled according to a gate input signal.

Abstract: Devices and circuits for voltage reference architectures that can increase the PSRR parameter by improving the saturation margin for an output transistor. For example, a device can include a current source coupled between a first power supply line and a circuit node, a voltage production circuit coupled between the circuit node and a second power supply line to produce a plurality of voltages respectively at voltage nodes thereof, a multiplexer coupled to the voltage nodes of the voltage production circuit and the output node and configured to select and output one of the voltages to the output node, and a control circuit configured to supply the one of the voltages to the circuit node.

Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

Abstract: A differential amplifier comprising a first upper device and a first lower device series coupled between two power supplies and a second upper device and a second lower device series coupled between the two power supplies. A first DC voltage enables the first upper device and the second upper device and a second DC voltage regulates current flow in the first lower device and the second lower device. An AC signal component is coupled to the first upper device and the second lower device while the AC signal complement is coupled to the first lower device and the second upper device. A first output signal between the first upper device and the first lower device. Separate RC networks couple the AC signals to their respective device. A first and second output signal forms between the upper device and the lower device, respectively. All the devices are same channel type.