Abstract: An embodiment of a circuit includes first and second branches, an amplifier, a compensation circuit, and a bias unit. The first and second branches are respectively operable to generate first and second currents. The amplifier has a first amplifier input node coupled to the first branch, a second amplifier input node coupled to the second branch, an amplifier output node coupled to the first and second branches, and a first compensation node. The compensation unit is operable to provide a first offset-compensation signal to the first compensation node. And the first bias unit is operable to provide first and second bias signals to the first and second input nodes, respectively, such that the amplifier is operable to cause the first current to approximately equal the second current.

Abstract: Provided is a constant current circuit and a reference voltage circuit with improved line regulation without needing a start-up circuit. The constant current circuit includes: a constant current generation circuit including NMOS transistors and a resistor; a current mirror circuit including a pair of depletion mode NMOS transistors, for allowing a current of the constant current generation circuit to flow; and a feedback circuit for maintaining constant voltages of source terminals of the pair of depletion mode NMOS transistors.

Abstract: An exponential multistage charge pump is provided wherein node voltages in a pumpcell in one stage of the charge pump are used to control operation of clock drivers in a subsequent stage of the charge pump.

Abstract: A beta enhancement circuit includes a current source connected in series with a transistor between two voltage supply lines. In an embodiment, the voltage supply lines are configured for connection to a power source and ground potential. A resistor device is connected between a control terminal of the transistor device and one of voltage supply lines. A value for the resistor device is selected based on one or more process dependent parameters of the transistor.

Abstract: A charge-pump circuit includes at least one flying capacitor stage having a capacitor with a first terminal selectively coupled between a negative voltage input through a first electronic switch and a negative voltage output through a second electronic switch. A second terminal of the capacitor is selectively coupled between a fixed voltage node through a third electronic switch and an error signal input through a fourth electronic switch. A positive voltage source is coupled to the negative voltage output through a feedback network. A feedback amplifier having an error signal output, a reference voltage input, and a feedback input is coupled to the feedback network. A switch controller having a first clock output drives the first electronic switch and the third electronic switch, while a second clock output drives the second electronic switch and the fourth electronic switch.

Abstract: A voltage operation system includes: a power on reset circuit, a voltage detecting circuit, an operating signal generating circuit, and an electronic fuse circuit. The power on reset circuit is used for generating a power on reset signal. The voltage detecting circuit detects an operating voltage to output a voltage detecting signal. The operating signal generating circuit, coupled to the power on reset circuit and the voltage detecting circuit-outputs an operating signal. The electronic fuse circuit can be fused according to a lock signal, a fuse signal, and the operating signal.

Abstract: A circuit used for indicating process corner and extreme temperature mainly comprises a proportional to absolute temperature (PTAT) current source, a negative to absolute temperature (NTAT) current source, a constant to absolute temperature (CTAT) current source, a corner detector, a poly detector, an extreme temperature detector. The circuit can improve more power consumption without trade-off. In debug phase, the circuit can read out a state of a suspect sample and can run simulation check quickly to identify the real problem. In production phase, the circuit can easily read out at a processing station. In the mean time, a large quantity of data can be easily collected and analyzed.

Abstract: An electronic fuse system includes: a pad, an electronic fuse circuit, a first switch circuit, and a control circuit. The pad is used for receiving a reference voltage. The electronic fuse circuit is used for changing a voltage level when a current signal passes. The first switch circuit is coupled between the pad and the electronic fuse circuit, for controlling the first switch circuit to be disabled or enabled according to a switch control signal. The control circuit, coupled to the first switch circuit is for transferring the switch control signal according a control signal and a lock signal.

Abstract: According to an example embodiment, an apparatus for controlling a power supply voltage for an integrated circuit may be provided, which may include a plurality of different types of process region detection circuits, each process region detection circuit configured to identify a respective process region of a plurality of process regions. The apparatus may also include a voltage selection circuit configured to determine a highest voltage among the voltages associated with the identified process regions and to select a power supply voltage for the integrated circuit that is equal to the highest voltage, one or more functional test circuits configured to perform a functional test using the selected power supply voltage, and a voltage adjuster circuit configured to increase the selected power supply voltage if the functional test fails.

Abstract: In one embodiment, a temperature compensation circuit includes a bias circuit configured to output a bias current having a current value increasing in proportion to an absolute temperature in a low-temperature region, and having a greater current value than the current value proportional to the absolute temperature in a high-temperature region, and a transistor which is supplied with the bias current. The bias circuit includes first to third transistors, a fourth transistor through which a first current flows, a fifth transistor, a sixth transistor through which a second current flows, and a control circuit having a connection terminal capable of being connected with an external resistor for adjusting a magnitude of the second current. The bias circuit generates a third current by adding the first current to the second current, and outputs the bias current that is the third current or a fourth current depending on the third current.

Abstract: A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs.

Abstract: In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.

Abstract: A circuit includes a PMOS body bias circuit including a PMOS charge pump for generating a positive supply voltage, a PMOS reference voltage generator for providing a PMOS reference voltage, and a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage. The circuit also includes a NMOS body bias circuit including a NMOS charge pump for generating a negative supply voltage, a NMOS reference voltage generator for providing a NMOS reference voltage, and a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage. The PMOS body bias voltage and the NMOS body bias voltage drive bulk of PMOS and NMOS devices in the integrated circuit.

Abstract: A semiconductor apparatus includes: a first transistor; a second transistor having a higher withstand voltage than the first transistor, a source of the second transistor coupled to a drain of the first transistor, a gate of the second transistor coupled to a source of the first transistor; a third transistor having a higher withstand voltage than the first transistor and a drain of the third transistor coupled to a drain of the second transistor; and a comparator that compares a source voltage of the first transistor with a source voltage of the third transistor, and controls a gate voltage of the first transistor.

Abstract: Disclosed are methods and systems for mitigating unwanted signal components. A received carrier signal is downconverted using a local reference signal that imposes an frequency perturbation or dither. Later, when an intermediate digitized signal is filtered to remove the DC offset that is an artifact of the sampling process, the dither in the carrier signal serves to distinguish the carrier from the unwanted offset. The preferred offset filter is a low pass filter with a passband that is narrow relative to the frequency range of the dither.

Abstract: For proximity detection, capacitance of a sensing element to ground is measured as one or more objects move into or out of proximity to the sensing element.

Abstract: The present invention provides a method and system for open loop compensation of delay variations in a delay line. The method includes sensing the Process, Voltage, Temperature (PVT) variations in the delay line using a sensing circuit. A first and second sensitive current are generated based on the PVT variations. The first and second sensitive currents are mirrored currents from the sensing circuit. Then, a first compensation current is generated based on the first sensitive current and a first summing current. The first summing current is a reference current independent of the PVT variations. Further, the first compensation current is mirrored as a second summing current and a second compensation current is generated from the second sensitive current and the second summing current. The second compensation current compensates the delay variations and has a sensitivity based on the sensitivities of the first and second sensitive currents.

Abstract: A charge pump system for low-supply voltage includes: a clock generator to generate a plurality of clock signals; a clock pump circuit coupled to said clock generator to generate high voltage; a level shifter coupled to said clock generator and said clock pump circuit to generate a plurality of HV (high voltage) clock signals; a main pump circuit coupled to said clock generator and said level shifter to generate output voltage.

Abstract: A wireless transceiver includes an antenna array that transmits an outbound RF signal containing outbound data to remote transceivers and that receives an inbound RF signal containing inbound data from the remote RF transceivers, wherein the antenna array is configurable based on a control signal. An antenna configuration controller generates the control signal to configure the antenna array to hop among a plurality of radiation patterns based on a hopping sequence. An RF transceiver section generates the outbound RF signal based on the outbound data and that generates the inbound data based on the inbound RF signal. In one configuration, a switching section selectively couples a selected one of the antennas in the array to the RF transceiver section, based on the control signal. In another configuration, the RF transceiver section includes an RF section for each antenna in the array.

Abstract: A circuit includes a first PMOS transistor and a second PMOS transistor, wherein a gate of the second PMOS transistor is coupled to a gate and a drain of the first PMOS transistor; a first NMOS transistor having a drain coupled to a drain of the first PMOS transistor; and a second NMOS transistor, wherein a drain of the second NMOS transistor is coupled to a gate of the first NMOS transistor, a gate of the second NMOS transistor, and a drain of the second PMOS transistor. A first switch is coupled between the drain of the first PMOS transistor and the drain of the second PMOS transistor. A second switch is coupled between a source of the first NMOS transistor and an electrical ground. A third switch is coupled between a source of the second NMOS transistor and the electrical ground.