Abstract: A method and system for processing Service Level Agreement (SLA) terms in a caching component in a storage system. The method can include monitoring cache performance for groups of data in the cache, each the group having a corresponding SLA. Overfunded SLAs can be identified according to the monitored cache performance. In consequence, an entry can be evicted from among one of the groups which correspond to an identified one of the overfunded SLAs. In one aspect of the present invention, the most overfunded SLA can be identified, and an entry can be evicted from among the group which corresponds to the most overfunded SLA.

Abstract: A system and method for pre-fetching data. A computer program comprising multiple basic blocks is submitted to a processor for execution. Tables or other data structures are associated with some or all of the basic blocks (e.g., a table is associated with, or stores, an instruction address of a particular basic block). During execution of a basic block, memory locations of data elements accessed during the executions are stored in the associated table. After a threshold number of executions, differences between memory locations of the data elements in successive executions are then computed. The differences are applied to the last stored memory locations to generate estimates of the locations for the data elements for a subsequent execution. Using the estimated locations, the data elements can be pre-fetched before, or as, the basic block is executed.

Abstract: A method and apparatus are described for providing an implicit write-back in a distributed shared memory environment implementing a snoop based architecture. A requesting node submits a single read request to a snoop based architecture controller switch. The switch recognizes that another node other than the requesting node and the home node for the desired data has a copy of the data. The switch directs the request to the responding node that is not the home node. The responding node, having modified the data, provides a single response back to the switch that causes the switch to both update the data at the home node and answer the requesting node. The updating of the data at the home node is done without receiving an explicit write instruction from the requesting node.

Abstract: In a computer system having a computer, a storage system having storage units being coupled to the computer and for storing user data used by the computer, and a backup device being coupled to the computer and the storage system, a backup method is presented for obtaining a backup of the data stored in the storage unit to the backup device. The storage system holds the user data dually in a first and a second storage units. In backing up the user data, a split instruction for releasing the duplex state of the first and the second storage units is sent from the computer to the storage unit. In response to the split instruction, the storage system interrupts the reflection of the update of the user data to the first storage unit onto the second storage unit. Then, a copy instruction for copying the user data held in the second storage unit to the backup device is sent from the computer to the storage system.

Abstract: A system and method of transporting volumes of information from one host computer system to another using point-in-time copies of LUNs but wherein the hardware provider does not necessarily understand the volume configuration of the data. The system and method involves an intermediate layer, i.e., a point-in-time copy interface layer that communicates with both a requesting host computer system and a hardware provider to enable the transfer of volumes of information without requiring that the hardware provider understand the volume information.

Abstract: A system and method are provided for moving information between cache coherent memory systems of a partitioned multiprocessor computer system while containing faults to a single partition. The multiprocessor computer system includes a plurality of processors, memory subsystems and input/output (I/O) subsystems that can be divided into a plurality of partitions. Each I/O subsystem includes at least one I/O bridge for interfacing between one or more I/O devices and the multiprocessor system. The I/O bridge has a data mover configured to retrieve information from a “source” partition and to store that information within its own “destination” partition. When activated, the data mover issues a request to the source partition for a non-coherent copy of the information. The home memory subsystem in the source partition preferably responds to the request by sending the data mover “valid”, but non-coherent copy of the information, e.g.

Abstract: A data processing system that provides a DMA Exclusive state that enables pipelining of Input/Output (I/O) DMA Write transactions. The data processing system includes a system processor, a system bus, a memory, a plurality of I/O components and an I/O processor. The data processing system further comprises operational protocol providing a pair of instructions/commands that are utilized to complete a DMA Write operation. The pair of instructions is DMA_Write_No_Data and DMA_Write With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire “DMA ownership” of a cache line that is to be written. The initial ownership of the cache line is marked by a weak DMA state (D1), which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations.

Abstract: A method and data processing system that supports pipelining of Input/Output (I/O) DMA Write transactions. An I/O processor's operational protocol is provided with a pair of instructions/commands that are utilized to complete a DMA Write operation. The instructions are DMA_Write_No_Data and DMA_Write_With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire ownership of a cache line that is to be written. The ownership of the cache line is marked by a weak DMA state, which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations. When each preceding DMA Write operation has completed or each corresponding DMA_Write_No_Data operation has been placed in a DMA Exclusive state, then the weak DMA state is changed to a DMA Exclusive state, which forces a retry of snooped operations until the write transaction to memory is completed.

Abstract: A programmable data path accelerator is described. The programmable data path accelerator operates on a file server that includes a network interface for communicating with one or more clients. The network interface includes a network transaction queue. A metafile processor is configured to communicate with the network interface across a first memory-mapped bus and is configured to communicate with the storage interface across a second memory-mapped bus. A data engine configured to communicate with the network interface across the first memory-mapped bus and to communicate with the storage interface across the second memory-mapped bus.

Abstract: Techniques for efficient memory management that enable rapid longest prefix match lookups in memory. In general, the present invention is efficacious wherever maintenance of a good distribution of holes in a sorted list is required. This technique relies on a proactive hole management methodology to preserve a good distribution of holes in each memory region in such a way that one does not have to search for holes in order to insert or store a new entry into the list. In particular, all holes in a given region are kept in one or more contiguous sub-region. Keeping the holes contiguous requires a hole move every time there is a delete operation. The amortized cost of these operations is justified by the resulting simplification in later insert (store) and delete operations. For example, during an insert the new entry is placed at the end of the contiguous sub-region of used entries in the region.

Abstract: A method for addressing a particular location of a memory organized as a plurality of words having an odd number (e.g., three) partitions. Upon receiving an address for a particular memory location, address translation circuitry according to the present invention effectively converts the address to a floating point number. The address translation circuitry then divides the received address by three to determine which word of memory—and which byte—is being addressed. In particular, the quotient of the division process provides the word address, while the remainder provides the byte offset. Memory addressed by the present invention may be organized into “words” of varying length. For example, each “word” may be ninety-six bits wide, with partitions of thirty-two bits each. In this embodiment, the remainder of the division process identifies a particular thirty-two bit partition.

Abstract: Method, program product, and system for the probabilistic determination of storage device enclosure-to-storage device relationships in a storage system, when the exact relationship is unknown. A table is built at storage system startup representing the initial storage device enclosure to storage device relationship. For efficiency, as topology changes occur within the storage system, the table is not updated to reflect the topology change. When a user wishes to access a specific storage device enclosure, the table is opened, and the most recently added storage device entry for the selected enclosure is chosen. The chosen storage device is queried for its current physical location. If the storage device still resides within the selected enclosure, the user access the enclosure via the chosen storage device.