Patents Examined by Thanh Nguyen
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Patent number: 8906798Abstract: A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.Type: GrantFiled: December 14, 2012Date of Patent: December 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Yu Wang, Tzu-Wei Chiu, Shin-Puu Jeng
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Patent number: 8907319Abstract: A light emitting device package includes a body having a cavity, at least one insulating layer disposed on the body, first and second electrode layers disposed on the insulating layer and electrically isolated from each other, at least one light emitting device disposed on a bottom surface of the cavity and electrically connected to the first and second electrode layer, a light-transmissive resin layer sealing the light emitting device disposed in the cavity, and a metal layer disposed on a rear surface of the body to face the light emitting device, wherein the light emitting device is grown in an m-direction on the (1123) plane of a substrate and includes a light emitting structure including a first conductive semiconductor layer, and active layer, and a second conductive semiconductor layer.Type: GrantFiled: December 11, 2012Date of Patent: December 9, 2014Assignee: LG Innotek Co., Ltd.Inventors: Hyeong Seon Yun, Eun Dk Lee
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Patent number: 8895981Abstract: A multichip module (MCM) has redundant I/O connections between its dice. That is, the number of inter-die I/O connections used is larger than the number of connections ordinarily used to provide connectivity between the dice. Defective connections are discovered through testing after MCM assembly and avoided, with signals being rerouted through good (e.g., not defective) redundant connections. The testing can be done at assembly time and the results stored in nonvolatile memory. Alternatively, the MCM can perform the testing itself dynamically, e.g., at power up, and use the test results to configure the inter-die I/O connections.Type: GrantFiled: December 28, 2011Date of Patent: November 25, 2014Assignee: Altera CorporationInventor: David Lewis
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Patent number: 8895453Abstract: A layer with a laterally varying thickness, a substrate with a first surface and an insulation layer formed on the first surface of the substrate is provided. A plurality of at least one of recesses and openings is formed in the insulation layer, wherein the plurality is arranged at a pitch. Each of the at least one of recesses and openings has a lateral width, wherein at least one of the pitch and the lateral width varies in a lateral direction. The plurality of the at least one of recesses and openings defines a given region in the insulation layer. The insulation layer having the plurality of the at least one of the recesses and openings is tempered at elevated temperatures so that the insulation layer at least partially diffluences to provide the insulation layer with a laterally varying thickness at least in the given region.Type: GrantFiled: April 12, 2013Date of Patent: November 25, 2014Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Johannes Laven, Holger Schulze
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Patent number: 8865541Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.Type: GrantFiled: December 19, 2013Date of Patent: October 21, 2014Assignee: Texas Instruments IncorporatedInventors: Farzan Farbiz, Akram A. Salman
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Patent number: 8860134Abstract: A trench power device includes a semiconductor layer, a trench gate structure, a trench source structure, and a contact. The semiconductor layer has an epitaxial layer, a doped body region, a S/D region, and a doped contact-carrying region. The doped body region is formed in the epitaxial layer, the S/D region is formed in the doped body region, and the doped contact-carrying region is formed in the doped body region and outside a projecting portion defined by orthogonally projecting from the S/D region to the doped body region. The trench gate structure is embedded in the S/D region, the doped body region, and the epitaxial layer. The trench source structure is embedded in the doped body region and the epitaxial layer, and is connected to the doped contact-carrying region. The contact is connected to the S/D region and the doped contact-carrying region.Type: GrantFiled: September 3, 2013Date of Patent: October 14, 2014Assignee: Sinopower Semiconductor, Inc.Inventor: Po-Hsien Li
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Patent number: 8853727Abstract: A high output light emitting diode (LED) based lighting module includes a plurality of LEDs on a substrate board, a fiber optic mounting assembly that securely holds a plurality of fiber bundles that form a fiber cable to said LEDs so that each LED mates to a fiber bundle making each fiber bundle slightly overlap the active area of its respective LED and mechanical means for holding each fiber optic bundle a fixed distance from said LED substrate.Type: GrantFiled: December 11, 2012Date of Patent: October 7, 2014Inventors: David Sanso, Mason Williams, Brent Hymel, Aaron Pitzer
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Patent number: 8853668Abstract: A light emitting device comprises a first layer having an n-type Group III-V semiconductor, a second layer adjacent to the first layer, the second layer comprising an active material that generates light upon the recombination of electrons and holes. The active material in some cases has one or more V-pits at a density between about 1 V-pit/?m2 and 30 V-pits/?m2. The light emitting device includes a third layer adjacent to the second layer, the third layer comprising a p-type Group III-V semiconductor.Type: GrantFiled: September 29, 2011Date of Patent: October 7, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Jeff Ramer, Steve Ting
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Patent number: 8847404Abstract: In a stacked chip configuration, the “inter chip” connection is established on the basis of functional molecules, thereby providing a fast and space-efficient communication between the different semiconductor chips.Type: GrantFiled: April 8, 2013Date of Patent: September 30, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Stephan Kronholz, Markus Lenski, Ralf Richter
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Integrated circuit configuration having extension conductor structure and fabricating method thereof
Patent number: 8835996Abstract: An integrated circuit configuration includes a substrate, a diffusion region, a gate structure, an extension conductor structure, a dielectric layer, a contact structure, and a metal conductor line. The diffusion region is formed in the substrate. The gate structure is formed over the substrate and spanned across the diffusion region. The extension conductor structure is formed over the semiconductor substrate and contacted with the diffusion region. The extension conductor structure is extended externally to a first position along a surface of the substrate, wherein the first position is outside the diffusion region. The dielectric layer is formed over the substrate, the gate structure and the extension conductor structure. The contact structure is penetrated through the dielectric layer to be contacted with the first position of the extension conductor structure. The metal conductor line is formed on the dielectric layer and contacted with the contact structure.Type: GrantFiled: December 28, 2011Date of Patent: September 16, 2014Assignee: United Microelectronics CorporationInventor: Chin-Sheng Yang -
Patent number: 8835225Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.Type: GrantFiled: December 4, 2013Date of Patent: September 16, 2014Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Fu-Di Tang, Ching-Chiuan Wei, Yung-Chih Lin
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Patent number: 8829690Abstract: A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.Type: GrantFiled: December 23, 2013Date of Patent: September 9, 2014Assignee: General Electric CompanyInventors: Paul Alan McConnelee, Kevin Matthew Durocher, Scott Smith, Laura A. Principe
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Patent number: 8828752Abstract: A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits.Type: GrantFiled: December 18, 2013Date of Patent: September 9, 2014Assignee: Manutius IP Inc.Inventor: Steve Ting
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Patent number: 8822243Abstract: A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling structure is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling structure is disposed adjacent to the first layer. An orifice formed in the light coupling structure extends to the first layer. An electrode formed in the orifice is in electrical communication with the first layer.Type: GrantFiled: January 14, 2014Date of Patent: September 2, 2014Assignee: Manutius IP Inc.Inventors: Li Yan, Chao-kun Lin, Chih-Wei Chuang
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Patent number: 8822988Abstract: In at least some embodiments, a thin-film transistor (TFT) includes a gate electrode and a gate dielectric covering the gate dielectric. The TFT also includes a source electrode and a drain electrode adjacent the gate dielectric. The TFT also includes a bi-layer channel between the source electrode and the drain electrode, the bi-layer channel having a zinc indium oxide (ZIO) layer positioned adjacent the gate dielectric and a zinc tin oxide (ZTO) layer that covers the ZIO layer.Type: GrantFiled: March 31, 2009Date of Patent: September 2, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Vincent C. Korthuis, Randy Hoffman
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Patent number: 8809203Abstract: It is an object to provide a method for manufacturing a semiconductor device that has a semiconductor element including a film in which mixing impurities is suppressed. It is another object to provide a method for manufacturing a semiconductor device with high yield. In a method for manufacturing a semiconductor device in which an insulating film is formed in contact with a semiconductor layer provided over a substrate having an insulating surface with use of a plasma CVD apparatus, after an inner wall of a reaction chamber of the plasma CVD apparatus is coated with a film that does not include an impurity to the insulating film, a substrate is introduced in the reaction chamber, and the insulating film is deposited over the substrate. As a result, an insulating film in which the amount of impurities is reduced can be formed.Type: GrantFiled: May 30, 2008Date of Patent: August 19, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Mitsuhiro Ichijo, Tetsuhiro Tanaka, Takashi Ohtsuki, Seiji Yasumoto, Kenichi Okazaki, Shunpei Yamazaki, Naoya Sakamoto
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Patent number: 8810031Abstract: An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.Type: GrantFiled: December 30, 2010Date of Patent: August 19, 2014Assignee: Industrial Technology Research InstituteInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Patent number: 8796864Abstract: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.Type: GrantFiled: June 14, 2013Date of Patent: August 5, 2014Assignee: Spansion LLCInventors: Naomi Masuda, Koji Taya
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Patent number: 8796769Abstract: A method including introducing a species into a substrate including semiconductor material; and translating linearly focused electromagnetic radiation across a surface of the substrate, the electromagnetic radiation being sufficient to thermally influence the species. An apparatus including an electromagnetic radiation source; a stage having dimensions suitable for accommodating a semiconductor substrate within a chamber; an optical element disposed between the electromagnetic radiation source and the stage to focus radiation from the electromagnetic radiation source into a line having a length determined by the diameter of a substrate to be placed on the stage; and a controller coupled to the electromagnetic radiation source including machine readable program instructions that allow the controller to control the depth into which a substrate is exposed to the radiation.Type: GrantFiled: September 14, 2012Date of Patent: August 5, 2014Assignee: Applied Matierials, Inc.Inventors: Dean C. Jennings, Amir Al-Bayati
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Patent number: 8786000Abstract: A method of manufacturing a semiconductor device includes: forming a core insulating film that includes first openings, on a semiconductor substrate; forming cylindrical lower electrodes that cover sides of the first openings with a conductive film; forming a support film that covers at least an upper surface of the core insulating film between the lower electrodes; forming a mask film in which an outside of a region where at least the lower electrodes are formed is removed, by using the support film; and performing isotropic etching on the core insulating film so as to leave the core insulating film at a part of an area between the lower electrodes, after the mask film is formed.Type: GrantFiled: December 28, 2011Date of Patent: July 22, 2014Assignee: PS4 Luxco S.A.R.L.Inventor: Eiji Hasunuma