Patents Examined by Thanh Nguyen
  • Patent number: 8778705
    Abstract: A light-emitting diode (“LED”) device has an LED chip attached to a substrate. The terminals of the LED chip are electrically coupled to leads of the LED device. Elastomeric encapsulant within a receptacle of the LED device surrounds the LED chip. A second encapsulant is disposed within an aperture of the receptacle on the elastomeric encapsulant.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: July 15, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Tong Fatt Chew
  • Patent number: 8779506
    Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Norbert Krischke
  • Patent number: 8772128
    Abstract: A single crystal semiconductor substrate is irradiated with ions that are generated by exciting a hydrogen gas and are accelerated with an ion doping apparatus, thereby forming a damaged region that contains a large amount of hydrogen. After the single crystal semiconductor substrate and a supporting substrate are bonded, the single crystal semiconductor substrate is heated to be separated along the damaged region. While a single crystal semiconductor layer separated from the single crystal semiconductor substrate is heated, this single crystal semiconductor layer is irradiated with a laser beam. The single crystal semiconductor layer undergoes re-single-crystallization by being melted through laser beam irradiation, thereby recovering its crystallinity and planarizing the surface of the single crystal semiconductor layer.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junpei Momo, Fumito Isaka, Eiji Higa, Masaki Koyama, Akihisa Shimomura
  • Patent number: 8766272
    Abstract: “An imaging device formed as an active pixel array combining a CMOS fabrication process and a nanowire fabrication process. The pixels in the array may include a single or multiple photogates surrounding the nanowire. The photogates control the potential profile in the nanowire, allowing accumulation of photo-generated charges in the nanowire and transfer of the charges for signal readout. Each pixel may include a readout circuit which may include a reset transistor, charge transfer switch transistor, source follower amplifier, and pixel select transistor. A nanowire is generally structured as a vertical rod on the bulk semiconductor substrate to receive light energy impinging onto the tip of the nanowire. The nanowire may be configured to function as either a photodetector or a waveguide configured to guild the light to the substrate. Light of different wavelengths can be detected using the imaging device.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Zena Technologies, Inc.
    Inventors: Young-June Yu, Munib Wober
  • Patent number: 8759970
    Abstract: An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: June 24, 2014
    Assignee: Round Rock Research, LLC
    Inventor: Salman Akram
  • Patent number: 8753962
    Abstract: When a mixed gas of trichlorosilane and dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 1000 to 1100° C., preferably, 1040 to 1080° C. When dichlorosilane is used as source gas, a silicon layer is epitaxially grown on a surface of a silicon wafer within a temperature range of 900 to 1150° C., preferably, 1000 to 1150° C. According to this, a silicon epitaxial wafer, which has low haze level, excellent flatness (edge roll-off), and reduced orientation dependence of epitaxial growth rate, and is capable of responding to the higher integration of semiconductor devices, can be obtained, and this epitaxial wafer can be used widely in production of semiconductor devices.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: June 17, 2014
    Assignee: Sumco Corporation
    Inventor: Naoyuki Wada
  • Patent number: 8748897
    Abstract: An array substrate for an organic electroluminescent display device includes a substrate including a display area and a non-display area; a gate line and a data line; a thin film transistor including a semiconductor layer of polycrystalline silicon, a gate insulating layer, a gate electrode, an inter insulating layer, a source electrode, and a drain electrode; auxiliary lines formed of a same material and on a same layer as the data line; a passivation layer of organic insulating material and including a drain contact hole exposing the drain electrode, and an auxiliary line contact hole exposing one of the auxiliary lines; and a first electrode and a line connection pattern on the passivation layer, wherein the first electrode contacts the drain electrode and the line connection pattern contacts the one of the first auxiliary pattern.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: June 10, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Hee-Dong Choi, Seung-Joon Jeon
  • Patent number: 8748307
    Abstract: A method for processing a wafer in accordance with various embodiments may include: forming a passivation over the wafer; forming a protection layer over at least a surface of the passivation facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation; forming a mask layer over at least a surface of the protection layer facing away from the wafer, wherein the mask layer includes a material that is selectively etchable to the material of the protection layer; etching the wafer using the mask layer as a mask; selectively etching the material of the mask layer to remove the mask layer from the protection layer, after etching the wafer; and selectively etching the material of the protection layer to remove the protection layer from the passivation, after selectively etching the material of the mask layer.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Joachim Hirschler, Gudrun Stranzl
  • Patent number: 8748860
    Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: June 10, 2014
    Assignee: SK Hynix Inc.
    Inventors: Su Jin Chae, Jin Hyock Kim, Young Seok Kwon
  • Patent number: 8748874
    Abstract: A protein photoelectric conversion device including a gold electrode; and a substance selected from the group consisting of a metal-substituted cytochrome b562, a zinc chlorin cytochrome b562, a derivative thereof, and a variant thereof immobilized on the gold electrode.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 10, 2014
    Assignee: Sony Corporation
    Inventors: Seiji Yamada, Yuichi Tokita, Yoshio Goto, Wei Luo, Satoshi Nakamaru
  • Patent number: 8749028
    Abstract: When a silicon through electrode is to be formed from a back surface (the surface on which a semiconductor device is not formed) of a silicon substrate, a wide range of an interlayer insulating film made of a Low-k material absorbs moisture, and there is a problem that the electrical characteristics of wiring are degraded. The above-described problem can be solved by forming at least a single ring-shaped frame laid out to enclose the silicon through electrode by using metal wirings in plural layers and a connection via connecting the upper and lower metal wirings in a Low-k material layer penetrated by the silicon through electrode and by forming a moisture barrier film made up of at least a metal wiring and a connection via between the silicon through electrode and a circuit wiring formed in the vicinity of the silicon through electrode.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: June 10, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Mayu Aoki, Kenichi Takeda, Kazuyuki Hozawa
  • Patent number: 8735209
    Abstract: An apparatus or method can include forming a graphene layer including a working surface, forming a polyvinyl alcohol (PVA) layer upon the working surface of the graphene layer, and forming a dielectric layer upon the PVA layer. In an example, the PVA layer can be activated and the dielectric layer can be deposited on an activated portion of the PVA layer. In an example, an electronic device can include such apparatus, such as included as a portion of graphene field-effect transistor (GFET), or one or more other devices.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 27, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Inanc Meric, Kenneth Shepard, Noah J. Tremblay, Philip Kim, Colin P. Nuckolls
  • Patent number: 8736044
    Abstract: To minimize the warpage of an organic substrate that supports at least one electrical hardware component (e.g., a system-in-package module), a bottom surface of a lid is attached to a top surface of the electrical hardware component. The lid includes a leg that extends from the bottom surface of the lid towards a top surface of the substrate. A portion of the leg closest to the substrate may move relative to the substrate. As the lid warps, the lid does not also cause distortion of the substrate. The leg may be a flange that extends at least a portion of the width or at least a portion of the length of the lid, may be a post located at the perimeter of the lid, or may be any other portion extending from above the electrical component towards the substrate.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: May 27, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Mudasir Ahmad, Kuo-Chuan Liu, Mohan Nagar, Bangalore Shanker
  • Patent number: 8716862
    Abstract: An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 ? or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: May 6, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ping Chen, Dian-Hau Chen
  • Patent number: 8716831
    Abstract: An eFuse structure having a first metal layer serving as a fuse with a gate including an undoped polysilicon (poly), a second metal layer and a high-K dielectric layer all formed on a silicon substrate with a Shallow Trench Isolation formation, and a process of fabricating same are provided. The eFuse structure enables use of low amounts of current to blow a fuse thus allowing the use of a smaller MOSFET.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: May 6, 2014
    Assignee: Broadcom Corporation
    Inventors: Xiangdong Chen, Wei Xia
  • Patent number: 8703533
    Abstract: A semiconductor package includes a substrate having a connection terminal with a groove on its surface. Nanopowder may be disposed on a bottom of the groove. A semiconductor chip may be flip-chip bonded to the substrate by the nanopowder. A filler member may be interposed between the substrate and the semiconductor chip.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 22, 2014
    Assignee: SK Hynix Inc.
    Inventor: Si Han Kim
  • Patent number: 8698163
    Abstract: A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 15, 2014
    Assignee: Toshiba Techno Center Inc.
    Inventor: Steve Ting
  • Patent number: 8691656
    Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
  • Patent number: 8674515
    Abstract: A structure of connecting at least two integrated circuits in a 3D arrangement by a metal-filled through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Mukta G. Farooq, Subramanian S. Iyer, Steven J. Koester, Huilong Zhu
  • Patent number: 8673727
    Abstract: A manufacturing method for manufacturing a flexible non-volatile memory is provided. The manufacturing method comprises the steps outlined below. A flexible substrate is provided. A planarization layer is formed on the flexible substrate. A metal bottom electrode layer is deposited on the planarization layer. A mask is formed to define a plurality of patterns. An AZTO layer having a plurality of electrically independent AZTO cells is deposited on the metal bottom electrode layer corresponding to the patterns. A top electrode layer is deposited on the AZTO layer corresponding to the AZTO cells to form a plurality of non-volatile memory cells.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: March 18, 2014
    Assignee: National Chiao Tung University
    Inventors: Po-Tsun Liu, Yang-Shun Fan