Patents Examined by Thanh Nguyen
  • Patent number: 8536655
    Abstract: Even in the case where negative current flows in a semiconductor device, the potential of a semiconductor substrate is prevented from becoming lower than the potential of a deep semiconductor layer which is a component of a circuit element, and a parasitic element is prevented from operating, which accordingly prevents malfunction of the semiconductor device. The semiconductor device includes the n-type semiconductor substrate, a power element, the circuit element, and an external circuit. The external circuit includes a power supply, a resistive element having one end connected to the power supply, and a diode having its anode electrode connected to the other end of the resistive element and its cathode electrode connected to the ground. To the other end of the resistive element, a semiconductor layer is connected.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: September 17, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Yamamoto, Atsunobu Kawamoto
  • Patent number: 8530305
    Abstract: Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Jaydeb Goswami
  • Patent number: 8525288
    Abstract: In the diffusion region (3) of the second conductivity mode, a more highly doped region of the same conductivity mode (5) is introduced in such a manner that the region of the first conductivity mode (2) which is covered by the metal silicide (9) and of the second conductivity mode (3) are connected in a conductive manner. The region (3) of the second conductivity mode is diffused in such a manner that it reaches the more highly doped region (1) of the first doping type (1), with an outward diffusion of the doping from the more highly doped substrate layer (1) into the more weakly doped layer (2) of the same conductivity mode in the direction of the semiconductor surface taking place at the same time.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: September 3, 2013
    Assignee: Eris Technology Corporation
    Inventors: Michael Reschke, Hans-Jurgen Hillemann, Klaus Gunther
  • Patent number: 8519521
    Abstract: An electronic device can include a packaging material having a first surface and a second surface opposite the first surface, and leads including die connection surfaces and external connection surfaces. The electronic device can further include a trench extending from an upper surface of the packaging substrate towards a lower surface of the packaging substrate, wherein a set of leads lie immediately adjacent to the trench, and the packaging material is exposed at the bottom of the trench. In an embodiment, an encapsulant is formed over the upper surface of the packaging substrate and within the trench. In a particular embodiment, the trenches may be formed before or after placing a die over the packaging substrate, or before or after forming electrical connections between the die and leads of the packaging substrate.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Shutesh Krishnan, Chee Hiong Chew, Jatinder Kumar
  • Patent number: 8507892
    Abstract: A method for forming a nanowire tunnel field effect transistor device includes forming a nanowire connected to a first pad region and a second pad region, the nanowire including a core portion and a dielectric layer, forming a gate structure on the dielectric layer of the nanowire, forming a first protective spacer on portions of the nanowire, implanting ions in a first portion of the exposed nanowire and the first pad region, implanting in the dielectric layer of a second portion of the exposed nanowire and the second pad region, removing the dielectric layer from the second pad region and the second portion, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity to connect the exposed cross sections of the nanowire to the second pad region.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 13, 2013
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Josephine B. Chang, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8507300
    Abstract: A method for making a lighting apparatus includes providing a substrate and disposing a light-emitting diode overlying the substrate. The light-emitting diode has a top surface oriented away from the substrate and a plurality of side surfaces. A light-conversion material is provided that includes a substantially transparent base material and a wave-shifting material dispersed in the base material. The concentration of the wave-shifting material can be at least 30%. In an embodiment, the concentration of the wave-shifting material can be approximately 50% or 70%. A predetermined amount of the light-conversion material is deposited on the top surface of the light-emitting diode while the side surfaces are maintained substantially free of the light-conversion material.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: August 13, 2013
    Assignee: LedEngin, Inc.
    Inventor: Yi Dong
  • Patent number: 8501561
    Abstract: Disclosed is a semiconductor component arrangement and a method for producing a semiconductor component arrangement. The method comprises producing a trench transistor structure with at least one trench disposed in the semiconductor body and with at least an gate electrode disposed in the at least one trench. An electrode structure is disposed in at least one further trench and comprises at least one electrode. The at least one trench of the transistor structure and the at least one further trench are produced by common process steps. Furthermore, the at least one electrode of the electrode structure and the gate electrode are produced by common process steps.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Franz Hirler, Norbert Krischke
  • Patent number: 8502366
    Abstract: A semiconductor package includes a body having a first surface and a second surface facing away from the first surface, and formed with a groove in the first surface. First connection parts may electrically connect a portion of the first surface to a portion of the second surface of the body. Second connection parts may electrically connect a portion of a bottom portion of the groove to a portion of the second surface of the body. A lower device may be disposed in the groove of the body, and have third connection parts that are electrically connected with the second connection parts. An upper device may be disposed on the body and the lower device, and have fourth connection parts that are electrically connected with the first connection parts and the third connection parts.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: August 6, 2013
    Assignee: SK Hynix Inc.
    Inventor: Seung Taek Yang
  • Patent number: 8502238
    Abstract: A nitride semiconductor laser device with a reduction in internal crystal defects and an alleviation in stress, and a semiconductor optical apparatus comprising this nitride semiconductor laser device. First, a growth suppressing film against GaN crystal growth is formed on the surface of an n-type GaN substrate equipped with alternate stripes of dislocation concentrated regions showing a high density of crystal defects and low-dislocation regions so as to coat the dislocation concentrate regions. Next, the n-type GaN substrate coated with the growth suppressing film is overlaid with a nitride semiconductor layer by the epitaxial growth of GaN crystals. Further, the growth suppressing film is removed to adjust the lateral distance between a laser waveguide region and the closest dislocation concentrated region to 40 ?m or more.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: August 6, 2013
    Assignees: Sharp Kabushiki Kaisha, Sumitomo Electric Industries, Ltd.
    Inventors: Shigetoshi Ito, Takayuki Yuasa, Yoshihiro Ueta, Mototaka Taneya, Zenpei Tani, Kensaku Motoki
  • Patent number: 8502376
    Abstract: A semiconductor package includes a carrier strip having a die cavity and bump cavities. A semiconductor die is mounted in the die cavity of the carrier strip. In one embodiment, the semiconductor die is mounted using a die attach adhesive. In one embodiment, a top surface of the first semiconductor die is approximately coplanar with a top surface of the carrier strip proximate to the die cavity. A metal layer is disposed over the carrier strip to form a package bump and a plated interconnect between the package bump and a contact pad of the first semiconductor die. An underfill material is disposed in the die cavity between the first semiconductor die and a surface of the die cavity. A passivation layer is disposed over the first semiconductor die and exposes a contact pad of the first semiconductor die. An encapsulant is disposed over the carrier strip.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: August 6, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Dioscoro A. Merilo, Lionel Chien Hui Tay, Jose A. Caparas
  • Patent number: 8492187
    Abstract: A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. The thickness of each sacrificial material layer of the stack increases upwards from the sacrificial material layer that is formed nearest to the base substrate. Because of this difference in thicknesses, each sacrificial material layer etches at different rates, with thicker sacrificial material layers etching faster than thinner sacrificial material layers. An etch is performed that first removes the thickest sacrificial material layer of the multilayered stack. The uppermost semiconductor device layer within the multilayered stack is accordingly first released. As the etch continues, the other sacrificial material layers are removed sequentially, in the order of decreasing thickness, and the other semiconductor device layers are removed sequentially.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Ning Li, Kuen-Ting Shiu
  • Patent number: 8492246
    Abstract: It is an object of the present invention to improve a factor which influences productivity such as variation caused by a characteristic defect of a circuit by thinning or production yield when an integrated circuit device in which a substrate is thinned is manufactured. A stopper layer is formed over one surface of a substrate, and an element is formed over the stopper layer, and then, the substrate is thinned from the other surface thereof. A method in which a substrate is ground or polished or a method in which the substrate is etched by chemical reaction is used as a method for thinning or removing the substrate.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Dairiki, Naoto Kusumoto, Takuya Tsurume
  • Patent number: 8486756
    Abstract: The semiconductor device according to the present invention has a planar semiconductor chip having projecting connection terminals provided on one surface thereof. A shelf is provided where a peripheral edge of a surface of the semiconductor chip opposite one surface thereof onto which connection terminals are provided is removed. This makes it possible to secure a larger volume of the fillet portion of the underfill, thereby helping improve the function of preventing the rising up of the excess underfill by providing a shelf in the semiconductor chip.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: July 16, 2013
    Assignee: Spansion LLC
    Inventors: Naomi Masuda, Koji Taya
  • Patent number: 8487444
    Abstract: A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies.
    Type: Grant
    Filed: December 4, 2009
    Date of Patent: July 16, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Oscar M. K. Law, Kuo H. Wu
  • Patent number: 8481422
    Abstract: A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: July 9, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Kelvin Chan, Khaled A. Elsheref, Alexandros T. Demos, Mei-Yee Shek, Lipan Li, Li-Qun Xia, Kang Sub Yim
  • Patent number: 8482033
    Abstract: In one embodiment, a semiconductor structure is provided which includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: July 9, 2013
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Ning Li, Kuen-Ting Shiu
  • Patent number: 8476767
    Abstract: A stacked layer type semiconductor device includes N memories each including at least one main via and (N?1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: July 2, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ho Cheol Lee
  • Patent number: 8470648
    Abstract: A semiconductor device including a plurality of field-effect transistors which are stacked with a planarization layer interposed therebetween over a substrate having an insulating surface, in which semiconductor layers in the plurality of field-effect transistors are separated from semiconductor substrates, and the semiconductor layers are bonded to an insulating layer formed over the substrate having an insulating surface or an insulating layer formed over the planarization layer.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: June 25, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideto Ohnuma, Tetsuya Kakehata
  • Patent number: 8466013
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, and forming a gate structure on the SOI substrate; etching an SOI layer and a BOX layer of the SOI substrates on both sides of the gate structure, so as to form trenches exposing the BOX layer and extending partially into the BOX layer; forming metal sidewall spacers on sidewalls of the trenches, wherein the metal sidewall spacers is in contact with the SOI layer under the gate structure; forming an insulating layer filling partially the trenches, and forming a dielectric layer to cover the gate structure and the insulating layer; etching the dielectric layer to form first contact through holes that expose at least partially the insulating layer, and etching the insulating layer from the first contact through holes to form second contact through holes that expose at least partially the metal sidewall spacer; filling the first contact through holes and the second contact through hol
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: June 18, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8461017
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: June 11, 2013
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu