Patents Examined by Thanh T. Nguyen
  • Patent number: 12218143
    Abstract: An array substrate and a manufacturing method thereof are provided. The array substrate includes a substrate, an active layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer. The array substrate includes a thin film transistor (TFT) area, and the second metal layer includes a source-drain metal sub-layer located in the TFT area. The TFT area is defined with an active layer exposed area. The array substrate includes a barrier layer, and an orthographic projection of the barrier layer on the active layer at least partially covers an orthographic projection of the active layer exposed area on the active layer.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: February 4, 2025
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Macai Lu, Jiangbo Yao
  • Patent number: 12217636
    Abstract: In the stretchable display device of the present disclosure, peeling and delamination of connection lines between adjacent circuits mounted on individual fixed substrates that might occur during stretching is reduced. According to one embodiment a temporary substrate is formed having a plurality of stiff areas and an elastic area, the temporary substrate being on a subsidiary substrate. A plurality of individual substrates are disposed on the lower substrate and located in the active area on the lower substrate. A first inorganic layer is formed on each of the plurality of individual substrates, the first inorganic layer having a sidewall surface extending upward from the first substrate. An organic layer is deposited overlying the first inorganic layer, including overlying the sidewall surface of the first inorganic layer.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: February 4, 2025
    Assignee: LG Display Co., Ltd.
    Inventors: Hyunju Jung, Eunah Kim
  • Patent number: 12219802
    Abstract: A display device comprises a display panel, a panel support member disposed on a surface of the display panel and including segments that are spaced apart from each other, and a reflective layer disposed between the segments.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: February 4, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Tae Jin Kong, Jin Yeong Kim, Jun Seok Min, Il You, Hae Ju Yun, Seon Beom Ji
  • Patent number: 12217966
    Abstract: There is provided a processing method of a wafer. The processing method includes a protective sheet preparation step of preparing a protective sheet including a first sheet that is thermocompression-bonded to a surface of the wafer by heating, a second sheet that is laid on the first sheet and has fluidity due to the heating, and a third sheet that is laid on the second sheet and keeps flatness even with the heating. The processing method also includes a protective sheet laying step of causing a side of the first sheet to face a front surface of the wafer and executing heating to execute thermocompression bonding to lay the protective sheet on the front surface of the wafer and a grinding step of causing a side of the protective sheet to be held by a holding surface of a chuck table and grinding a back surface of the wafer.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: February 4, 2025
    Assignee: DISCO CORPORATION
    Inventor: Kazuma Sekiya
  • Patent number: 12211707
    Abstract: A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Ying-Ju Chen
  • Patent number: 12199085
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: January 14, 2025
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Sairam Agraharam, Shengquan Ou, Thomas J De Bonis, Todd Spencer, Yang Sun, Guotao Wang
  • Patent number: 12194570
    Abstract: There is provided a laser processing method for cutting a semiconductor object along a virtual plane facing a surface of the semiconductor object in the semiconductor object. The laser processing method includes a first step of forming a plurality of first modified spots along the virtual plane by causing laser light to enter into the semiconductor object from the surface, and a second step of forming a plurality of second modified spots along the virtual plane so as not to overlap the plurality of first modified spots, by causing laser light to enter into the semiconductor object from the surface.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 14, 2025
    Assignees: National University Corporation Tokai National Higher Education and Research System, HAMAMATSU PHOTONICS K.K.
    Inventors: Atsushi Tanaka, Chiaki Sasaoka, Hiroshi Amano, Daisuke Kawaguchi, Yotaro Wani, Yasunori Igasaki
  • Patent number: 12193245
    Abstract: An imaging device includes pixels. Each of the pixels includes a counter electrode, a pixel electrode, and a photoelectric conversion layer that includes carbon nanotubes. The pixels include a first pixel and a second pixel adjacent to the first pixel. The pixel electrode of the first pixel and the pixel electrode of the second pixel are isolated from each other. Carbon nanotubes included in the photoelectric conversion layer in at least one selected from the group consisting of the first pixel and the second pixel include at least one first carbon nanotube that satisfies A<B, where A denotes length of a carbon nanotube in a direction in which the pixel electrode of the first pixel and the pixel electrode of the second pixel are arranged and B denotes length of a gap between the pixel electrode of the first pixel and the pixel electrode of the second pixel.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: January 7, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Sanshiro Shishido, Yasuo Miyake
  • Patent number: 12191263
    Abstract: A semiconductor structure includes a chip structure and a sealing structure disposed on a substrate of the semiconductor structure. The sealing structure includes a metal wall body and a blocking wall body located on a top of the metal wall body, and the metal wall body and the blocking wall body both are disposed around the chip structure.
    Type: Grant
    Filed: January 16, 2022
    Date of Patent: January 7, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengmeng Wang, Hsin-Pin Huang
  • Patent number: 12183646
    Abstract: A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: December 31, 2024
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En Luan
  • Patent number: 12176352
    Abstract: An electronic device is provided. The electronic device includes at least two non-recesses, a recess and an organic layer. The recess is disposed between the at least two non-recesses. The at least two non-recesses and the recess are formed in an insulating layer. The organic layer is disposed on the at least two non-recesses and in the recess. The organic layer includes an end which is in contact with one of the at least two non-recesses.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: December 24, 2024
    Assignee: Innolux Corporation
    Inventors: Ardour Chang, Joe Huang
  • Patent number: 12166021
    Abstract: Provided is a method of manufacturing a micro light emitting device array. The method includes forming a display transfer structure including a transfer substrate and a plurality of micro light emitting devices, where the transfer substrate includes at least two first alignment marks; preparing a driving circuit board, the driving circuit board including a plurality of driving circuits and at least two second alignment marks, arranging the display transfer structure and the driving circuit board to face each other so that the at least two first alignment marks and the at least two second alignment marks face one another and bonding the plurality of micro light emitting devices of the display transfer structure to the plurality of driving circuits.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: December 10, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungwook Hwang, Junsik Hwang, Hyunjoon Kim, Joonyong Park, Seogwoo Hong
  • Patent number: 12165966
    Abstract: A package including a device die and an encapsulant is provided. The device die includes a semiconductor substrate, an interconnect structure, a conductive via, and a dielectric layer. The interconnect structure is disposed over the semiconductor substrate. The conductive via is disposed over and electrically coupled to the interconnect structure. The dielectric layer is disposed over the interconnect structure and laterally encapsulating the conductive via, wherein the dielectric layer includes a sidewall and a bottom surface facing the interconnect structure, and the sidewall of the dielectric layer is tilted with respect to the bottom surface of the dielectric layer. The encapsulant laterally encapsulates the device die.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Che Tu, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 12133375
    Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate and a plurality of discrete bit line structures located on the substrate, the bit line structure having a metal layer therein, a top surface of the metal layer being lower than a top surface of the bit line structure; forming a first isolation film filled between the adjacent bit line structures, a top surface of the first isolation film being higher than the top surface of the metal layer and lower than the top surface of the bit line structure; forming a first dielectric film on the top and sidewalls of the bit line structure and on the top surface of the first isolation film; and etching to remove the first dielectric film on the top of the bit line structures and the top surface of the first isolation film to form a first dielectric layer, and etching to remove the first isolation film exposed by the first dielectric layer to form a first isolation layer exactly below the first dielectric layer.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: October 29, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiao Zhu
  • Patent number: 12125786
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: October 22, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Patent number: 12107004
    Abstract: A semiconductor structure including a self-assembled monolayer for enhancing metal-dielectric adhesion and preventing metal diffusion is provided. The semiconductor structure includes a substrate and a first dielectric layer on the substrate. A contact structure is embedded in the first dielectric layer and includes a conductive line. The semiconductor structure further includes a self-assembled monolayer on the conductive line, and a second dielectric layer on the first dielectric layer and the conductive line. The self-assembled monolayer is chemically bonded to the conductive line and the second dielectric layer.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Zhen Yu Guan, Hsun-Chung Kuang
  • Patent number: 12100673
    Abstract: A semiconductor device includes a first circuit element over a substrate; a fill material over the substrate and in contact with sides of the first circuit element; and a dishing resistant (DR) structure in the fill material and outside a perimeter of the first circuit element. Some DR structures are dummy structures manufactured in the fill material over the substrate.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Chia-En Huang
  • Patent number: 12094837
    Abstract: A method of manufacturing a semiconductor device includes: forming grooves in a front side surface of a wafer; filling the grooves with a first side face protection material; thinning the wafer at a backside surface of the wafer opposite the front side surface; depositing a backside metallization layer over the backside surface of the thinned wafer; and laser cutting along the grooves through the side face protection material and through the backside metallization layer to separate the wafer into multiple semiconductor devices.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: September 17, 2024
    Assignee: Infineon Technologies AG
    Inventors: Christian Gruber, Benjamin Bernard, Tobias Polster, Carsten von Koblinski
  • Patent number: 12087748
    Abstract: A display device having a pad area and a display area is provided. The display device includes: a substrate; a pad structure on the substrate in the pad area; and a display element part on the substrate in the display area. The pad structure includes a first pad pattern, a second pad pattern on the first pad pattern, and a third pad pattern on the second pad pattern, and the display element part includes a light emitting element configured to emit light in a display direction. The second pad pattern has a first area and a second area, the second pad pattern and the third pad pattern do not contact each other in the first area, and the second pad pattern and the third pad pattern contact each other in the second area.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: September 10, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jong Hwan Cha
  • Patent number: 12087824
    Abstract: A novel material is provided. A composite oxide semiconductor includes a first region and a second region. The first region contains indium. The second region contains an element M (the element M is one or more of Ga, Al, Hf, Y, and Sn). The first region and the second region are arranged in a mosaic pattern. The composite oxide semiconductor further includes a third region. The element M is gallium. The first region contains indium oxide or indium zinc oxide. The second region contains gallium oxide or gallium zinc oxide. The third region contains zinc oxide.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: September 10, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuharu Hosaka, Yukinori Shima, Junichi Koezuka, Kenichi Okazaki