Patents Examined by Thanh V Pham
  • Patent number: 10096616
    Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including electrodes vertically stacked on a substrate, a channel structure coupled to the electrodes to constitute a plurality of memory cells three-dimensionally arranged on the substrate, the channel structure including first vertical channels and second vertical channels penetrating the stack structure and a first horizontal channel disposed under the stack structure to laterally connect the first vertical channels and the second vertical channels to each other, a second horizontal channel having a first conductivity type and connected to a sidewall of the first horizontal channel of the channel structure, and conductive plugs having a second conductivity type and disposed on top ends of the second vertical channels.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: October 9, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Lee, Heonkyu Lee, Shinhwan Kang, Youngwoo Park
  • Patent number: 10043800
    Abstract: An integrated circuit device includes a substrate including a device active region, a fin-type active region protruding from the substrate on the device active region, a gate line crossing the fin-type active region and overlapping a surface and opposite sidewalls of the fin-type active region, an insulating spacer disposed on sidewalls of the gate line, a source region and a drain region disposed on the fin-type active region at opposite sides of the gate line, a first conductive plug connected the source or drain regions, and a capping layer disposed on the gate line and extending parallel to the gate line. The capping layer includes a first part overlapping the gate line, and a second part overlapping the insulating spacer. The first and second parts have different compositions with respect to each other. The second part contacts the first part and the first conductive plug.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 7, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhwa Kim, Kyungin Choi, Hwichan Jun, Inchan Hwang
  • Patent number: 9978730
    Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: May 22, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chan Yoo, Todd O. Bolken
  • Patent number: 9972544
    Abstract: A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first fin pattern and the second fin pattern; a field insulating film partially filling the first trench, an upper surface of the field insulating film being lower than an upper surface of the first fin pattern and an upper surface of the second fin pattern; a spacer spaced apart from the first fin pattern and the second fin pattern, the spacer being on the field insulating film and defining a second trench, the second trench including an upper portion and an lower portion; an insulating line pattern on a sidewall of the lower portion of the second trench; and a conductive pattern filling an upper portion of the second trench and being on the insulating line pattern.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 15, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju Youn Kim, Ji Hwan An, Tae Won Ha, Se Ki Hong
  • Patent number: 9966566
    Abstract: A display device and a method of manufacturing the display device are disclosed. In one aspect, the display device includes a substrate including a display region and a peripheral region. A first block member is in the peripheral region and surrounding display structures, the first block member having a first height. A second block member is spaced apart from the first block member in a first direction extending from the display region to the peripheral region, the second block member surrounding the first block member, the second block member having a second height that is greater than the first height. A first encapsulation layer is over the display structures, the first block member, and the second block member. A second encapsulation layer is over the first encapsulation layer, the second encapsulation layer overlapping at least a portion of the first block member in the depth dimension of the display device.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: May 8, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sung-Young Shin
  • Patent number: 9960171
    Abstract: Semiconductor devices are provided. A semiconductor device includes a plurality of gate electrodes. The semiconductor device includes a channel structure adjacent the plurality of gate electrodes. The semiconductor device includes a plurality of charge storage segments between the channel structure and the plurality of gate electrodes. Methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: May 1, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kohji Kanamori, Shinhwan Kang, Youngwoo Park, Junghoon Park
  • Patent number: 9954007
    Abstract: It is an object to manufacture a highly reliable display device using a thin film transistor having favorable electric characteristics and high reliability as a switching element. In a bottom gate thin film transistor including an amorphous oxide semiconductor, an oxide conductive layer having a crystal region is formed between an oxide semiconductor layer which has been dehydrated or dehydrogenated by heat treatment and each of a source electrode layer and a drain electrode layer which are formed using a metal material. Accordingly, contact resistance between the oxide semiconductor layer and each of the source electrode layer and the drain electrode layer can be reduced; thus, a thin film transistor having favorable electric characteristics and a highly reliable display device using the thin film transistor can be provided.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshinari Sasaki, Junichiro Sakata, Masashi Tsubuku
  • Patent number: 9933643
    Abstract: A curved display device comprising a display panel having a display surface on which a plurality of pixel units are disposed. The display surface includes a first bending line, which extends in a first direction, and a second bending line, which extends in a second direction that crosses the first direction at a right angle, and is bent along each of the first bending line and the second bending line.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: April 3, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jong Ho Chong, Su Young Kim, Eun Jung Lee
  • Patent number: 9935122
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsunehiro Ino, Daisuke Matsushita, Yasushi Nakasaki, Misako Morota, Akira Takashima, Kenichiro Toratani
  • Patent number: 9911756
    Abstract: To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided to overlap with a dicing line. A layer whose band gap is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.7 eV and less than or equal to 3.5 eV is provided around the semiconductor device such as a transistor. The layer may be in a floating state or may be supplied with a specific potential.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: March 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Yuto Yakubo, Shuhei Nagatsuka
  • Patent number: 9905733
    Abstract: A light-emitting device comprises a light-emitting semiconductor stack comprising a plurality of recesses and a mesa, each of the plurality of recesses comprising a bottom surface, and the mesa comprising an upper surface; a first electrode formed on the upper surface of the mesa; a plurality of second electrodes respectively formed on the bottom surface of the plurality of recesses; a first electrode pad formed on the light-emitting semiconductor stack and contacting with the first electrode; a second electrode pad formed on the light-emitting semiconductor stack and contacting with the plurality of second electrode; a first insulating layer comprising a plurality of passages to expose the plurality of second electrodes; and a second insulating layer comprising a plurality of spaces and formed on the first insulating layer, wherein the plurality of spaces is covered by the first electrode pad.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 27, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Hong-Che Chen, Chien-Fu Shen, Chao-Hsing Chen, Yu-Chen Yang, Jia-Kuen Wang, Chih-Nan Lin
  • Patent number: 9905583
    Abstract: The present invention provides an array substrate and a manufacturing method thereof, and a display apparatus. The array substrate comprises a gate layer, a gate insulating layer, an active layer, a source and drain layer, a scanning line and a signal line formed on a substrate, the signal line is provided in a same layer as the gate layer, the scanning line is provided in a same layer as the source and drain layer, the gate insulating layer is provided between the gate layer, the signal line and the active layer. The array substrate further comprises a first through hole and a second through hole penetrating through the gate insulating layer, the signal line is connected to the source and drain layer via the first through hole, and the scanning line is connected to the gate layer via the second through hole.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: February 27, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Li Zhang, Liangchen Yan, Jiangbo Chen
  • Patent number: 9899436
    Abstract: An image sensor includes a semiconductor substrate with at least one recess disposed on its surface and in the photosensitive area defined on the surface of the semiconductor substrate, a first-conductivity-type doped region disposed in the semiconductor substrate and in the photosensitive area, and a second-conductivity-type doped region disposed on the surface of the first-conductivity-type doped region and on the surface of the recess. A photosensitive device of the image sensor is formed of the first-conductivity-type doped region and the second-conductivity-type doped region.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 20, 2018
    Assignee: Powerchip Technology Corporation
    Inventors: Shih-Ping Lee, Yu-An Chen, Hsiu-Wen Huang, Chuan-Hua Chang
  • Patent number: 9899307
    Abstract: A fan-out chip package comprises a chip, an encapsulating layer, a first passivation layer, a redistribution wiring layer, a second passivation layer, and a plurality of vertical connectors. The encapsulation encapsulates the sides of the chip. The thickness of the encapsulation is the same as the thickness of the chip. The first passivation layer covers the active surface of the chip and the peripheral surface of the encapsulation. The redistribution layer is formed on the first passivation layer to extend the electrical connection of the chip to the peripheral surface of the encapsulation. The second passivation layer is formed on the first passivation layer. The vertical connectors are embedded in the encapsulation and the redistribution layer. The vertical connectors are only penetrate through the encapsulation protect the redistribution layer from damages.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: February 20, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Kuo-Ting Lin, Chia-Wei Chang
  • Patent number: 9899536
    Abstract: A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor device which includes a first oxide semiconductor layer which is in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which serves as a main current path (channel) of a transistor is provided. The first oxide semiconductor layer serves as a buffer layer for preventing a constituent element of the source and drain electrode layers from diffusing into the channel. By providing the first oxide semiconductor layer, it is possible to prevent diffusion of the constituent element into an interface between the first oxide semiconductor layer and the second oxide semiconductor layer and into the second oxide semiconductor layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: February 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Yukinori Shima, Hajime Tokunaga
  • Patent number: 9893311
    Abstract: An organic light-emitting diode (OLED) display panel includes an OLED substrate, and an OLED device arranged on the OLED substrate; a package cover; a hydrophobic barricade, which is arranged on an outer side of an OLED device corresponding to the package cover by means of screen printing. The hydrophobic barricade encloses the OLED device when the OLED substrate and the package cover are cemented together. A support is arranged on an outer side of the hydrophobic barricade arranged on the package cover by means of screen printing, and the support encloses the hydrophobic barricade. The support and the hydrophobic barricade are formed through screen printing with the same screen-printing template that includes two patterned apertures respectively corresponding to the support and the hydrophobic barricade.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: February 13, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Wei Yu
  • Patent number: 9887272
    Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: February 6, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Richard Kenneth Oxland, Martin Christopher Holland, Krishna Kumar Bhuwalka
  • Patent number: 9882132
    Abstract: The disclosed in the present disclosure is an evaporation equipment and an evaporating method. The evaporation equipment may include: a support, which is arranged for loading a substrate to be evaporated; and a zone temperature controlling device, which includes at least two temperature controlling parts and at least one temperature controlling device. A loading surface of the support may include a plurality of zones, and each of the plurality of zones may correspond to an evaporation region of the substrate to be evaporated. And each of the plurality of zones may be arranged with a temperature controlling part, and the temperature controlling device may be configured to control temperatures provided by the temperature controlling parts, so as to control corresponding deposition rates of film coating on the evaporation regions.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: January 30, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Haidong Wu, Qun Ma, Taegyu Kim
  • Patent number: 9881937
    Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li, Fee Li Lie, Derrick Liu, Chun Wing Yeung
  • Patent number: 9865609
    Abstract: A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and electrically coupled in series, where the transistors comprise a floating gate. An interconnect structure overlies the pair of transistors. A shield is arranged in the interconnect structure, directly over the floating gate. The shield is configured to block ions in the interconnect structure from moving to the floating gate. A method for manufacturing an OTP memory cell with floating gate shielding is also provided.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Lin Chen, Shyh-Wei Cheng, Che-Jung Chu