Patents Examined by Thao P. Le
  • Patent number: 10658261
    Abstract: A semiconductor device includes a first semiconductor element having an upper electrode and a lower electrode, a first upper heat sink connected to the upper electrode, and a first lower heat sink connected to the lower electrode. The first lower heat sink is opposed to the first upper heat sink such that the first semiconductor element is sandwiched between the upper and lower heat sinks. One of the first upper heat sink and the first lower heat sink is a laminated substrate having an insulator substrate (such as a ceramic substrate) and conductor layers disposed on opposite surfaces of the insulator substrate, and the other of the first upper heat sink and the first lower heat sink is a conductor plate that is a conductor having higher thermal conductivity than the insulator substrate.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 19, 2020
    Assignee: Denso Corporation
    Inventor: Takanori Kawashima
  • Patent number: 10658586
    Abstract: Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: James S. Clarke, Ravi Pillarisetty, Uday Shah, Tejaswi K. Indukuri, Niloy Mukherjee, Elijah V. Karpov, Prashant Majhi
  • Patent number: 10658387
    Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Zuoguang Liu, Xin Miao
  • Patent number: 10658466
    Abstract: A semiconductor element includes: a semiconductor substrate of a first conduction type; a silicon carbide semiconductor layer of the first conduction type disposed above a principal surface of the semiconductor substrate; a terminal edge region of a second conduction type disposed in the silicon carbide semiconductor layer; an insulating film; a first electrode disposed on the silicon carbide semiconductor layer; and a seal ring surrounding the first electrode. The terminal edge region is disposed to surround part of a surface of the silicon carbide semiconductor layer when viewed in a normal direction of the principal surface of the semiconductor substrate. The terminal edge region includes a guard ring region of the second conduction type, and a terminal edge injection region of the second conduction type. The seal ring is formed on the terminal edge injection region through an opening disposed on the insulating film.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 19, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Masao Uchida
  • Patent number: 10651377
    Abstract: The present disclosure provides a storage element, a storage device, a method for manufacturing the same and a driving method. The method for manufacturing the storage element includes: providing a substrate; preparing a thin film transistor on the substrate; and preparing a storage functional pattern by using a phase change material, in which the storage functional pattern is connected to a drain electrode of the thin film transistor.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 12, 2020
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ruiyong Wang, Lianjie Qu, Ruizhi Yang, Yang You
  • Patent number: 10651279
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Yi Yang, Ching-Fu Yeh, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 10651290
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: May 12, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
  • Patent number: 10643963
    Abstract: A semiconductor structure and its fabrication method are provided. The fabrication method includes: providing a base substrate including a wiring region and an isolation region. A patterned layer is formed on the isolation region of the base substrate and the patterned layer exposes the wiring region of the base substrate. After forming the patterned layer, a redistribution layer is formed on the wiring region of the based substrate exposed by the patterned layer. A protective layer is formed on the redistribution layer, and after forming the protective layer, the patterned layer is removed.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: May 5, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Feng Ping Cai
  • Patent number: 10634955
    Abstract: A display panel includes a first display substrate, a second display substrate facing and spaced apart from the first display substrate, a non-conductive sealing member disposed between the first display substrate and the second display substrate and formed around an outer perimeter of the display panel, a conductive sealing member disposed inside the non-conductive sealing member when viewed in a plan view, and a connection pad coupled to a side surface of the first display substrate and a side surface of the non-conductive sealing member. A signal line includes an end portion overlapping with the non-conductive sealing member and connected to the connection pad.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: April 28, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Saeron Park, Seungki Song
  • Patent number: 10636784
    Abstract: A display device includes a substrate; a plurality of pixels on the substrate; a drive circuit on the substrate; a first terminal and a second terminal connected to the pixels or the drive circuit and arranged on the substrate; a first wiring having a first end part connected with the first terminal, and a second end part located on an end part of the substrate; a second wiring having a third end part connected with the second terminal, and a fourth end part located on an end part of the substrate; a first current blocking unit blocking a current flowing in a direction from the second end part to the first end part of the first wiring; and a second current blocking unit blocking a current flowing in a direction from the fourth end part to the third end part of the second wiring.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: April 28, 2020
    Assignee: Japan Display Inc.
    Inventor: Naohisa Andou
  • Patent number: 10629629
    Abstract: The present disclosure provides an array substrate, a method for manufacturing the array substrate and a display device. The array substrate includes a base substrate and a signal line provided in a display region at a first side of the base substrate, an electrode is provided at a second side of the base substrate, the second side of the base substrate is opposite to the first side of the base substrate, a via-hole penetrating through the base substrate is provided at a position of the base substrate at which the electrode is provided, a connecting electrode is provided in the via-hole, and the signal line is electrically connected to the electrode provided at the second side of the base substrate through the connecting electrode.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: April 21, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yingwei Liu, Qi Yao, Zhiwei Liang
  • Patent number: 10629846
    Abstract: A display apparatus includes a flexible substrate and a first insulation layer disposed on the flexible substrate. The flexible substrate includes a bending area. The first insulation layer includes a first unevenness disposed over the bending area. The first unevenness includes two or more steps in at least a portion of the first unevenness.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hyekyung Park
  • Patent number: 10629835
    Abstract: Disclosed are an organic light emitting display device and lighting apparatus for vehicles using the same. The organic light emitting display device includes a first layer including a first organic layer and a first emission layer on a first electrode, a second layer including a second emission layer and a second organic layer on the first layer, a second electrode on the second layer, and a third organic layer between the first layer and the second layer. A thickness of the first emission layer is equal to or greater than a thickness of each of the first organic layer and the second organic layer.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 21, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventor: SeHee Lee
  • Patent number: 10622314
    Abstract: A chip package structure includes a substrate, a die, a plurality of warpage retainers, and an encapsulant. The substrate has a surface, on which the die is provided. The warpage retainers are provided at at least one corner of the substrate. The encapsulant covers the surface of the substrate, the die and the warpage retainers.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: April 14, 2020
    Assignee: MEDIATEK INC.
    Inventor: You-Wei Lin
  • Patent number: 10622073
    Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: April 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Xiang-Zheng Bo, Patrick R. Smith, Douglas T. Grider
  • Patent number: 10615182
    Abstract: A thin film transistor device and a method for preparing the same, an array substrate and a display device are disclosed. The thin film transistor device includes a first thin film transistor and a second thin film transistor coupled with each other. A first electrode of the first thin film transistor, a second electrode of the second thin film transistor, and a connecting line therebetween which is configured to couple the first electrode and the second electrode, are formed in a same layer, with each end of the connecting line being connected between respective ends of the first electrode and the second electrode opposite to each other. In the thin film transistor device, the first electrode and the second electrode are spaced apart from each other by a concave portion which is recessed in a region therebetween.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: April 7, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jideng Zhou, Ran Zhang, Yi Wang, Huanyu Li
  • Patent number: 10615206
    Abstract: An image-sensor module includes an image sensor and a protective layer that covers a subregion of an image-sensor surface of the image sensor, where at least two edge regions of the image-sensor surface, for example, edge regions situated at opposite edges of the image sensor, are not covered by the protective layer.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: April 7, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Christoph Decker, Johannes Eschler, Martin Reiche, Nikolai Bauer, Thomas Braune
  • Patent number: 10600837
    Abstract: An electric field imaging device is provided with which it is possible to visualize as a dynamic state an electromagnetic field intensity distribution and a phase delay/advance distribution in the vicinity of a product, using a sample of the actual product without lead-out lines. The electric field imaging device includes: an antenna which accepts a high-frequency signal emitted by the sample as an input; an electrooptic (EO) crystal plate which is a frequency fRF high-frequency electric field sensor; a flashing light source which radiates polarized light onto the EO crystal plate; an optical system leading to an analyzer for detecting phase changes in polarized light obtained by means of the EO crystal plate; an image capturing device which converts an in-plane distribution of optical beam from the analyzer into an electrical signal; and an information processing device which processes and displays an output signal from the image capturing device.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 24, 2020
    Assignee: NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATIONS TECHNOLOGY
    Inventor: Masahiro Tsuchiya
  • Patent number: 10600707
    Abstract: A fiber-containing resin substrate includes a thermosetting epoxy resin-impregnated fiber base material, and an uncured resin layer formed on one side thereof formed from a composition containing: (A) a crystalline bisphenol A type epoxy resin and/or a crystalline bisphenol F type epoxy resin, (B) an epoxy resin that is non-fluid at 25° C. other than the component (A), (C) a phenol compound having two or more phenolic hydroxy groups in one molecule, (D) an inorganic filler, and (E) an urea-based curing accelerator. The fiber-containing resin substrate collectively encapsulates a semiconductor devices mounting surface or a semiconductor devices forming surface on a wafer level, even when a large-diameter wafer or a large-diameter substrate is encapsulated, to reduce warpage of the substrate or the wafer and peeling of a semiconductor device from the substrate, and to have the uncured resin layer excellent in storage stability and handleability before curing.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 24, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yoshihiro Tsutsumi, Shuichi Fujii, Kenji Hagiwara, Shinsuke Yamaguchi
  • Patent number: 10593630
    Abstract: A semiconductor package includes a semiconductor die, a plurality of conductive bumps, a shielding layer, an encapsulant and a redistribution layer. The semiconductor die has an active surface, a backside surface and a lateral surface. The conductive bumps are disposed on the active surface of the semiconductor die. The shielding layer is disposed on the lateral surface of the semiconductor die. The encapsulant covers the shielding layer, and has a first surface and a second surface opposite to the first surface. The redistribution layer is disposed on the first surface of the encapsulant and electrically connected to the semiconductor die through the conductive bumps. The shielding layer is electrically connected to the redistribution layer.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: March 17, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsu-Nan Fang, Chun-Jun Zhuang, Yung I. Yeh