Patents Examined by Thao P. Le
  • Patent number: 10505111
    Abstract: A method is presented for reducing heat loss to adjacent semiconductor structures. The method includes forming a plurality of conductive lines within an interlayer dielectric, forming a barrier layer over at least one conductive line of the plurality of conductive lines, forming a via extending to a top surface of the barrier layer, and defining dual air gaps within the via and over the barrier layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Wei Wang
  • Patent number: 10497827
    Abstract: A light emitting device package includes a first frame and a second frame disposed to be spaced apart from each other; a body disposed between the first and second frames and comprising a recess; a first adhesive on the recess; a light emitting device on the first adhesive; a second adhesive disposed between the first and second frames and the light emitting device; and a resin portion disposed to surround the second adhesive and a partial region of the light emitting device.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: December 3, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Tae Sung Lee, June O Song, Ki Seok Kim, Young Shin Kim, Chang Man Lim
  • Patent number: 10497783
    Abstract: The invention provides a semiconductor structure and a method of preparing a semiconductor structure, which solves the problems of easy cracking, large warpage and large dislocation density which exist in a semiconductor compound epitaxial structure epitaxially grown on a substrate in the prior art. The semiconductor structure includes: a substrate; at least one periodic structure disposed over the substrate; wherein each of the periodic structures includes at least one period, each period including a first periodic layer and a second periodic layer which are sequentially stacked in an epitaxial direction.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 3, 2019
    Assignee: ENKRIS SEMICONDUCTOR, INC
    Inventors: Peng Xiang, Kai Cheng
  • Patent number: 10497735
    Abstract: The invention relates to an image sensor and method for reducing image defects. A photoconversion area is formed in a semiconductor layer. An insulating layer formed over the semiconductor layer contains a metal element. A lens over the insulting layer is positioned opposite the photoconversion area to focus light on it. A layer of light-absorbing material is deposited on the side of the metal element facing the lens to prevent reflection of parasitic light rays within the image device.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: December 3, 2019
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Axel Crocherie, Etienne Mortini, Jean Luc Huguenin
  • Patent number: 10497709
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: December 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima
  • Patent number: 10483371
    Abstract: A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a gate dielectric layer on the substrate; forming a dielectric barrier layer structure on the gate dielectric layer, a first silicon source gas being used to dope silicon in the dielectric barrier layer structure; forming a work function layer on the dielectric barrier layer structure; forming a gate barrier layer structure on the work function layer, a second silicon source gas being used to dope silicon in the gate barrier layer structure; and forming a gate electrode layer on the gate barrier layer structure.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: November 19, 2019
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Hao Deng
  • Patent number: 10453764
    Abstract: The present disclosure relates to wafer level packages including one or more semiconductor dies and a method of manufacturing the same. A method comprises: providing a carrier having a predetermined area, disposing a semiconductor device on the predetermined area, and forming a sacrificial wall on a periphery of the predetermined area.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: October 22, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-An Chen, Po-Wei Lu, Ming Tsung Shen, Yu-Tzu Peng
  • Patent number: 10454067
    Abstract: A display panel includes a base substrate including a front surface and a rear surface and having first and second holes, and a pixel layer on the base substrate. A display area is defined in the front surface. The first hole overlaps with the display area and penetrates the front and rear surfaces. The second hole overlaps with the display area, is adjacent to the first hole, and is recessed from the front surface. The base substrate includes a first base layer including the rear surface, a first barrier layer on the first base layer and including first inorganic films having a first refractive index, and second inorganic films having a second refractive index, a second base layer on the first barrier layer, and a second barrier layer on the second base layer and including the front surface. The first and second inorganic films are alternately stacked.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: October 22, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junghan Seo, Wooyong Sung
  • Patent number: 10444583
    Abstract: A display device includes a first gate line and a data line intersecting each other, a pixel electrode, a switching element comprising a gate electrode connected to the first gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode, and a connecting portion which connects the drain electrode with the pixel electrode, and a distance between the data line and the connecting portion is less than a distance between the data line and the gate electrode in a first direction perpendicular to the data line.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaemin Seong, Kyunghee Kim
  • Patent number: 10446561
    Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Kee-Sang Kwon, Do-Hyoung Kim, Bo-Un Yoon, Keun-Hee Bai, Kwang-Yong Yang, Kyoung-Hwan Yeo, Yong-Ho Jeon
  • Patent number: 10439074
    Abstract: A semiconductor device with improved electrical characteristics is provided. A semiconductor device with improved field effect mobility is provided. A semiconductor device in which the field-effect mobility is not lowered even at high temperatures is provided. A semiconductor device which can be formed at low temperatures is provided. A semiconductor device with improved productivity can be provided. In the semiconductor device, there is a range of a gate voltage where the field-effect mobility increases as the temperature increases within a range of the gate voltage from 0 V to 10 V. For example, such a range of a gate voltage exists at temperatures ranging from a room temperature (25° C.) to 120° C. In the semiconductor device, the off-state current is kept extremely low (lower than or equal to the detection limit of a measurement device) within the above temperature range.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 8, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Masashi Tsubuku, Satoru Saito, Noritaka Ishihara
  • Patent number: 10431591
    Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced form the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Akira Goda, Yushi Hu
  • Patent number: 10431661
    Abstract: Techniques are disclosed for forming a transistor with one or more additional spacers, or inner-gate spacers, as referred to herein. The additional spacers may be formed between the gate and original spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion, a middle portion, and an upper portion. In some such cases, the lower and upper portions of the gate may be wider between the original spacers than the middle portion of the gate, which may be as a result of the additional spacers being located between the middle portion of the gate and the original spacers. In some such cases, the gate may approximate an I-shape, -shape, -shape, ?-shape, L-shape, or ?-shape, for example.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: October 1, 2019
    Assignee: INTEL CORPORATION
    Inventors: En-Shao Liu, Joodong Park, Chen-Guan Lee, Jui-Yen Lin, Chia-Hong Jan
  • Patent number: 10424616
    Abstract: Integrated circuit devices including vertical Hall elements and lateral Hall elements and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit device includes a substrate including a lateral element region and a vertical element region. The integrated circuit device includes a well in the lateral element region and in the vertical element region of the substrate. Further, the integrated circuit device includes an insulating layer disposed over the substrate in the lateral element region, a semiconductor-over-insulator (SOI) semiconductor layer disposed over the insulating layer in the lateral element region, and lateral element conductive taps located in the semiconductor layer, wherein a lateral Hall element is defined in the lateral element region. Also, the integrated circuit device includes vertical element taps located in the well in the vertical element region, wherein a vertical Hall element is defined in the vertical element region.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: September 24, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Yongshun Sun, Eng Huat Toh
  • Patent number: 10424546
    Abstract: An electromagnetic interference absorber for an integrated circuit is provided. The absorber includes a geometric ring of electromagnetic energy absorbing material, dimensioned to fit over a ball grid array (BGA) integrated circuit package assembled to a substrate. The geometric ring has at least one projection arranged to fit into a gap between the substrate and a body of the BGA integrated circuit package so as to retain the geometric ring to the BGA integrated circuit package. Methods to contain electromagnetic interference and to manufacture an electromagnetic interference absorber are also provided.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: September 24, 2019
    Assignee: ARISTA NETWORKS, INC.
    Inventors: Duong Lu, Jiayi Wu, Robert Wilcox, Richard Hibbs, Paul Miller
  • Patent number: 10418433
    Abstract: Provided is a display device, including: a substrate; signal lines including a gate line, a data line, and a driving voltage line that collectively define an outer boundary of a pixel area; a transistor connected to the signal line; a first electrode extending across the pixel area and formed on the signal line and the transistor, and connected to the transistor, the first electrode having a first portion overlying only the signal line and the transistor, and a second portion comprising all of the first electrode not included in the first portion; a pixel defining layer formed on only the first portion of the first electrode; an organic emission layer formed on substantially the entire second portion but not on the first portion; and a second electrode formed on the pixel defining layer and the organic emission layer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: September 17, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Joung-Keun Park, Ki Wan Ahn, Joo Sun Yoon
  • Patent number: 10418442
    Abstract: Provided is a trench gate MOSFET including a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a first conductive layer of a second conductivity type, a second conductive layer and an interlayer insulating layer. The epitaxial layer is disposed on the substrate and has at least one trench therein. The first conductive layer is disposed in the lower portion of the trench and in physical contact with the epitaxial layer. The second conductive layer is disposed in the upper portion of the trench. The interlayer insulating layer is disposed between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: September 17, 2019
    Assignee: UBIQ Semiconductor Corp.
    Inventors: Chin-Fu Chen, Yi-Yun Tsai
  • Patent number: 10410950
    Abstract: Memory devices having heat spreaders are disclosed herein. In one embodiment, a memory device includes first memories coupled to a front side of a substrate, second memories coupled to a back side of the substrate, and a flexible heat spreader. The flexible heat spreader can include graphite and is coupled to back side surfaces of the first and second memories to dissipate heat generated by the first and second memories.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: George E. Pax
  • Patent number: 10403512
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: September 3, 2019
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
  • Patent number: 10403602
    Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner