Abstract: A display apparatus includes: a glass substrate; a light emitting device included in a pixel structure disposed on one principal surface of the glass substrate; an input electrode, disposed on the one principal surface, for inputting a driving signal to the light emitting device; and a back connection member disposed on the other principal surface of the glass substrate so as to be electrically connected to the input electrode. A back insulating layer is disposed on the other principal surface, and a top face of the back insulating layer is located above a top face of the back connection member.

Abstract: A display device may including: a substrate including a pixel area and a peripheral area; pixels provided in the pixel area of the substrate, each of the pixels including a light-emitting element provided with a pixel electrode; scan lines and data lines coupled to the pixels; a power line configured to supply driving power to the light-emitting elements, and extending in one direction; and an initialization power line configured to supply initialization power to the light-emitting elements. The power line and the initialization power line may be provided on different layers. The initialization power line may include: first conductive lines extending in a direction oblique to the scan lines and the data lines; and conductive lines intersecting the first conductive lines. The first and second conductive lines may be disposed in areas between the pixel electrodes of adjacent light-emitting elements.

Abstract: A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.

Abstract: A display device includes a first subpixel including a light-emitting layer of a first color, a second subpixel adjacent to the first subpixel in a row direction or a column direction, the second subpixel including a light-emitting layer of a second color, and a third subpixel adjacent to the first subpixel and the second subpixel in a diagonal direction, the third subpixel including a light-emitting layer of a third color, wherein the first subpixel to the third subpixel include light-emitting regions that are geometrically similar to one another, the light-emitting regions of two of the first subpixel to the third subpixel are in the same size, and a light-emitting region of remaining one of the first subpixel to the third subpixel is larger than the light-emitting regions of the two of the first subpixel to the third subpixel.

Abstract: A wiring line is provided on a TFT layer, in which the wiring line is formed in the same layer and formed of the same material as those of a reflection electrode. The reflection electrode includes a plurality of metallic conductive layers made up of a low resistance metallic material, an oxide-based lower transparent conductive layer provided on a lower surface side of a lowermost metallic conductive layer constituting a lowermost layer, an oxide-based upper transparent conductive layer having light reflectivity and provided on an upper surface side of an uppermost metallic conductive layer constituting an uppermost layer, and an oxide-based intermediate transparent conductive layer provided between the plurality of metallic conductive layers.

Abstract: A number of new solutions for enhancing the extraction of waveguided mode and suppressing surface plasmon polariton mode in OLEDs are disclosed.

Abstract: A display device includes a display region including a plurality of first regions, and a plurality of second regions arranged with a certain gap between the plurality of first regions, wherein each of the plurality of first regions includes a transistor, a first organic layer, a wiring, a first organic insulating layer on the wiring and the transistor, a display element on the first organic insulating layer, a first sealing layer on the display element and stacked in order with a first inorganic insulating layer, a second organic insulating layer and a second inorganic insulating layer, each of the plurality of second regions includes the wiring, a second organic layer on the wiring, a second sealing layer stacked in order with the first inorganic insulating layer and the second inorganic insulating layer, and a thickness of the second organic layer is smaller than the thickness of the first organic layer.

Abstract: A light-emitting device (100) includes a substrate (110), a first electrode (120), an auxiliary electrode (124), an insular conductive layer (126), an insulating layer (170), an organic layer (130), and a second electrode (140). The first electrode (120) is formed over the substrate (110), and is formed using a transparent conductive material. The auxiliary electrode (124) is formed over the first electrode (120). The conductive layer (126) is formed over the first electrode (120), and is formed of the same material as that of the auxiliary electrode (124). The insulating layer (170) is formed over a portion of the first electrode (120), and covers the auxiliary electrode (124) and the conductive layer (126). The organic layer (130) is formed over the first electrode (120), and the second electrode (140) is formed over the organic layer (130).

Abstract: The embodiments herein are directed to technologies for backside security meshes of semiconductor packages. One package includes a substrate having a first interconnect terminal of a first type and a second interconnect terminal of a second type. The package also includes a first security mesh structure disposed on a first side of an integrated circuit die and a conductive path coupled between the first interconnect terminal and the second interconnect terminal. The first security mesh structure is coupled to the first interconnect terminal and the second interconnect terminal being coupled to a terminal on a second side of the integrated circuit die.

Abstract: A method for manufacturing an electro-optical device according to the present disclosure includes bonding a counter substrate to a substrate, cutting a first portion by irradiation of a laser beam, and removing the first portion, wherein during cutting of the first portion, a first surface and a second surface sandwiching the first portion in plan view are formed by the irradiation of the laser beam, one or both of the first surface and the second surface is inclined with respect to a first plate surface, and a first distance between the first surface and the second surface in the first plate surface is greater than a second distance between the first surface and the second surface in a second plate surface, on the substrate side, of the counter substrate.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

Abstract: An optoelectronic component includes an optoelectronic semiconductor chip that generates primary radiation during intended operation of the semiconductor chip, which primary radiation is coupled out via an emission side of the semiconductor chip, an optical element on the emission side and including a plurality of transmission fields arranged laterally side by side, wherein each transmission field is individually and independently electrically controllable, the transmission fields each include an electrochromic material, the transmission fields are such that, by electrically driving a transmission field, the transmittance of the electrochromic material for a radiation coming from the direction of the semiconductor chip during operation is changed and transmittance of the optical element in the region of the respective transmission field is changed for the respective radiation.

Abstract: Embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes a plurality of sub-pixels, each sub-pixel of the plurality of sub-pixels defined by adjacent pixel-defining layer (PDL) structures with inorganic overhang structures disposed on the PDL structures, each sub-pixel having an anode, organic light-emitting diode (OLED) material disposed on the anode, and a cathode disposed on the OLED material. The device is made by a process including the steps of: depositing the OLED material and the cathode by evaporation deposition, and depositing an encapsulation layer disposed over the cathode.

Abstract: An epitaxial silicon wafer includes: a silicon wafer doped with phosphorus as a dopant and having an electrical resistivity of less than 1.0 m ?·cm; and an epitaxial film formed on the silicon wafer. The silicon wafer includes: a main surface to which a (100) plane is inclined; and a [100] axis that is perpendicular to the (100) plane and inclined at an angle ranging from 0°30? to 0°55? in any direction with respect to an axis perpendicular to the main surface. The epitaxial silicon wafer has at most 1/cm2 of a density of a hillock defect generated thereon.

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.

Abstract: A method may include providing a substrate, the substrate comprising a substrate base and a patterning stack, disposed on the substrate base. The substrate may include first linear structures in the patterning stack, the first linear structures being elongated along a first direction; and second linear structures in the patterning stack, the second linear structures being elongated along a second direction, the second direction forming a non-zero angle with respect to the first direction. The method may also include selectively forming a set of sidewall spacers on one set of sidewalls of the second linear structures.

Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.

Abstract: A bezel-free display comprises a display substrate and an array of pixels. Pixel rows and pixel columns are separated by row and column distances and connected by row and column lines, respectively. A column driver is electrically connected to each of the column lines and a row driver is electrically connected to each of the row lines. Row-connection lines are electrically connected to each of the row lines or row drivers. In certain embodiments, each pixel in the column of pixels closest to a display substrate edge is spatially separated from the edge by a distance less than or equal to the column distance. At least one row driver is spatially separated from the corresponding row by a distance less than the column or row distance, at least one column driver is spatially separated from the corresponding column by a distance less than the column or row distance, or both.

Abstract: A method of manufacturing a semiconductor device. A pre first semiconductor pattern having a crystalline semiconductor material is formed on a base substrate. A pre first insulation layer is formed on the pre first semiconductor pattern. A first semiconductor pattern is formed by defining a channel region in the pre first semiconductor pattern. A pre protection layer is formed on the pre first insulation layer. A pre second semiconductor pattern including an oxide semiconductor material is formed on the pre protection layer. A pre second insulation layer is formed on the pre second semiconductor pattern. The pre second insulation layer is patterned using an etching gas such that at least a portion of the pre second semiconductor pattern is exposed. A second semiconductor pattern is formed by defining a channel region in the pre second semiconductor pattern.

Abstract: An active matrix light emitting display comprising an anode layer comprising a plurality of individual selectively energizable anodes, a cathode layer comprising a plurality of individual selectively energizable cathodes, an emitter layer for emitting light when energized disposed between the anode layer and the cathode layer, and a photoluminescent layer comprising a plurality of various color photoluminescent pixels, wherein a selected anode and a selected cathode are energizable to photoexcite a selected color pixel. A light emitting device comprising, a light emitting photonic crystal having organic electroluminescent emitter material disposed within the photonic crystal, and a photoluminescent material disposed upon a surface of the light emitting photonic crystal, such that light emitted by the light emitting photonic crystal causes photoexcitation within the photoluminescent material.