Patents Examined by Thao X. Le
-
Patent number: 11127726Abstract: According to a flexible light-emitting device production method of the present disclosure, after an intermediate region (30i) and flexible substrate regions (30d) of a plastic film (30) of a multilayer stack (100) are divided from one another, the interface between the flexible substrate regions (30d) and a glass base (10) is irradiated with lift-off light. The multilayer stack (100) is separated into a first portion (110) and a second portion (120) while the multilayer stack (100) is in contact with a stage (210). The first portion (110) includes a plurality of light-emitting devices (1000) which are in contact with the stage (210). The light-emitting devices (1000) include a plurality of functional layer regions (20) and the flexible substrate regions (30d). The second portion (120) includes the glass base (10) and the intermediate region (30i).Type: GrantFiled: May 9, 2018Date of Patent: September 21, 2021Assignee: SAKAI DISPLAY PRODUCTS CORPORATIONInventors: Katsuhiko Kishimoto, Kazunobu Mameno, Kohichi Tanaka
-
Patent number: 11121165Abstract: One or more cross-wafer capacitors are formed in an electronic component, circuit, or device that includes stacked wafers. One example of such a device is a stacked image sensor. The image sensor can include two or more wafers, with two wafers that are bonded to each other each including a conductive segment adjacent to, proximate, or abutting a bonding surface of the respective wafer. The conductive segments are positioned relative to each other such that each conductive element forms a plate of a capacitor. A cross-wafer capacitor is formed when the two wafers are attached to each other.Type: GrantFiled: May 31, 2018Date of Patent: September 14, 2021Assignee: Apple Inc.Inventors: Chiajen Lee, Xiaofeng Fan
-
Patent number: 11112659Abstract: An array substrate includes a display region and a wiring region. The wiring region includes a plurality of sets of signal line leads and a plurality of wiring regions, and a same set of signal line leads extends to a same bonding region disposed in the wiring region. The wiring region further includes at least one auxiliary wiring structure. Each auxiliary wiring structure is disposed between adjacent two sets of signal line leads and includes a peripheral closed wiring loop. Each peripheral closed wiring loop includes a plurality of corner portion, and a shape of at least one corner portion proximate to the display region is a curve.Type: GrantFiled: June 28, 2018Date of Patent: September 7, 2021Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Guohua Wang, Wenming Ren, Fei Gao
-
Patent number: 11114650Abstract: According to a flexible OLED device production method of the present disclosure, after an intermediate region (30i) and flexible substrate regions (30d) of a plastic film (30) of a multilayer stack (100) are divided from one another, the interface between the flexible substrate regions (30d) and a glass base (10) is irradiated with laser light. The multilayer stack (100) is separated into a first portion (110) and a second portion (120) while the multilayer stack (100) is in contact with a stage (212). The first portion (110) includes a plurality of OLED devices (1000) which are in contact with the stage (212). The OLED devices (1000) include a plurality of functional layer regions (20) and the flexible substrate regions (30d). The second portion (120) includes the glass base (10) and the intermediate region (30i).Type: GrantFiled: October 26, 2017Date of Patent: September 7, 2021Assignee: Sakai Display Products CorporationInventors: Kohichi Tanaka, Katsuhiko Kishimoto
-
Patent number: 11107988Abstract: The present disclosure relates to a resistive random access memory device and a preparing method thereof.Type: GrantFiled: December 20, 2018Date of Patent: August 31, 2021Assignees: Research and Business Foundation Sungkyunkwan University, Global Frontier Center for Multiscale Energy SystemsInventors: Hyun Suk Jung, Sang Myeong Lee, Byeong Jo Kim, Jae Bum Jeon, Gi Joo Bang, Won Bin Kim, Dong Geon Lee
-
Patent number: 11108015Abstract: Provided is a long-life organic electroluminescent illumination panel which is flexible and, even when a load is applied by bending, impact or vibration, can suppress the occurrence of defects in an electrode layer and an organic layer containing an organic electroluminescent material, and which can suppress the occurrence of dark spots due to short circuiting. This organic electroluminescent illumination panel includes: a pair of electrode layers, at least one of which is transparent, between a flexible film substrate and a flexible film sealing material, at least one of which is transparent; and an organic layer containing an organic electroluminescent material which is sandwiched between the pair of electrode layers. This organic electroluminescent illumination panel has multiple spacers which are disposed on an electrode layer laminated on the flexible film substrate so as to pass through the organic layer and another electrode layer.Type: GrantFiled: February 26, 2019Date of Patent: August 31, 2021Assignee: HotaluX, Ltd.Inventor: Yoshikazu Sakaguchi
-
Patent number: 11101258Abstract: According to a flexible light-emitting device production method of the present disclosure, after an intermediate region (30i) and a flexible substrate region (30d) of a plastic film (30) of a multilayer stack (100) are divided, the interface between the plastic film (30) and a glass base (10) is irradiated with lift-off light. The multilayer stack (100) is separated into the first portion (110) and the second portion (120) while the multilayer stack (100) is kept in contact with the stage (212). The first portion (110) includes the intermediate region (30i) and a light-emitting device (1000) which are adhered to the stage (212). The light-emitting device (1000) includes a functional layer region (20) and the flexible substrate region (30d). The second portion (120) includes the glass base (10). The intermediate region (30i) adhered to the stage (212) is removed from the stage while the light-emitting device (1000) is kept adhered to the stage.Type: GrantFiled: May 9, 2018Date of Patent: August 24, 2021Assignee: SAKAI DISPLAY PRODUCTS CORPORATIONInventors: Katsuhiko Kishimoto, Kohichi Tanaka
-
Patent number: 11101238Abstract: A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.Type: GrantFiled: March 20, 2018Date of Patent: August 24, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Ming-Kai Liu, Chun-Lin Lu, Kai-Chiang Wu, Shih-Wei Liang, Ching-Feng Yang, Yen-Ping Wang, Chia-Chun Miao
-
Patent number: 11094879Abstract: Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element.Type: GrantFiled: September 4, 2018Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Andrea Gotti, F. Daniel Gealy, Innocenzo Tortorelli, Enrico Varesi
-
Patent number: 11094697Abstract: Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.Type: GrantFiled: November 7, 2018Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventors: Gloria Yang, Suraj J. Mathew, Raghunath Singanamalla, Vinay Nair, Scott J. Derner, Michael Amiel Shore, Brent Keeth, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
-
Patent number: 11088355Abstract: There is provided a method of manufacturing a display unit. The method includes forming a plurality of first electrodes, forming a functional layer that covers from the first electrode to an inter-electrode region, and locally applying an energy ray to the functional layer to form a disconnecting section or a high-resistance section in the functional layer in the inter-electrode region.Type: GrantFiled: April 2, 2019Date of Patent: August 10, 2021Assignee: SONY CORPORATIONInventor: Takashi Sakairi
-
Patent number: 11088348Abstract: An organic EL display device (100) includes a plurality of pixels, and also includes an element substrate including organic EL elements (3) respectively located in the plurality of pixels and a bank layer (48) defining each of the pixels; and a thin film encapsulation structure (10) covering the plurality of pixels. The thin film encapsulation structure includes a first inorganic barrier layer (12) and an organic barrier layer (14) in contact with a top surface or a bottom surface of the first inorganic barrier layer. The plurality of pixels include a red pixel, a green pixel and a blue pixel. The organic EL display device further includes a polydiacetylene layer (52) selectively provided on a second inorganic barrier layer (16) of the thin film encapsulation structure on the blue pixel and exhibiting a blue color. The polydiacetylene layer is a polymer of 10,12-pentacosadiynoic acid.Type: GrantFiled: January 31, 2018Date of Patent: August 10, 2021Assignee: SAKAI DISPLAY PRODUCTS CORPORATIONInventors: Katsuhiko Kishimoto, Takuji Kato
-
Patent number: 11081550Abstract: A tunnel field-effect transistor has a stacked structure including a second active region, a first active region, and a control electrode. The first active region includes a first-A active region and a first-B active region between the first-A active region and a first active region extension portion. A second active region exists below the first-A active region, and the second active region does not exist below the first-B active region. Where an orthographic projection image of the second active region and an orthographic projection image of the first active region overlap with each other is defined as L2-Total, and a length in a Y direction of the first active region is defined as L1-Y, when an axial direction of the first active region is defined as an X direction, and a stacked direction of the stacked structure is defined as a Z direction, L1-Y<L2-Total is satisfied.Type: GrantFiled: November 17, 2017Date of Patent: August 3, 2021Assignee: Sony Semiconductor Solutions CorporationInventor: Koichi Matsumoto
-
Patent number: 11075249Abstract: This organic EL display device (100) is provided with an element substrate which comprises multiple pixels and which comprises organic EL elements (3) arranged in each pixel and bank layers (48) defining the pixels, and a thin-film sealing structure (10) which covers the pixels. The thin-film sealing structure includes a first inorganic barrier layer (12), and an organic barrier layer (14) in contact with the upper surface or lower surface of the first inorganic barrier layer. The multiple pixels include red pixels, green pixels and blue pixels, and further have a first polydiacetylene layer (52a) which exhibits a blue color and which is provided selectively on a second inorganic barrier layer (16) of the thin-film sealing structure on blue pixels, and a second polydiacetylene layer (52b) which exhibits a red color and which is provided selectively on the thin-film sealing structure on red pixels. The first and second polydiacetylene layers are a polymer of 10,12-pentacosadiynoic acid.Type: GrantFiled: January 31, 2018Date of Patent: July 27, 2021Assignee: SAKAI DISPLAY PRODUCTS CORPORATIONInventors: Katsuhiko Kishimoto, Takuji Kato
-
Patent number: 11067856Abstract: A display apparatus comprises a first substrate comprising a first external surface and a first internal surface; a second substrate having a second external surface and a second internal surface facing the first internal surface of the first substrate; and a display unit disposed between the first and second substrates and comprising an array of pixels. The first substrate comprises a first side connecting the first external surface and the first internal surface. In a cross section perpendicular to the first external surface, the first side comprises a first straight region and a first curved region located between the straight region and the first internal surface. The second substrate comprises a second side connecting the first external surface and the first internal surface. The second side comprises a second straight region and a second curved region located between the straight region and the second internal surface.Type: GrantFiled: May 1, 2020Date of Patent: July 20, 2021Assignee: Samsung Display Co., Ltd.Inventors: Hyoengki Kim, Sangwook Sin, Jaeyoung Shin, Seungjoon Yoo, Jaeman Lee, Hyunsoo Lee, Beomjun Cheon, Gwangjoon Hong
-
Patent number: 11069701Abstract: A semiconductor memory device includes a first conductive layer, second conductive layers extending in a first direction and stacked above the first conductive layer in a second direction, a third conductive layer between the first conductive layer and the second conductive layers, a memory pillar extending inside the second conductive layers in the second direction, a first insulating layer that isolates the second conductive layers in a third direction, and second insulating layers spaced from an end of the first insulating layer and extending in the third direction. The second insulating layers are spaced from an extension line of the first insulating layer that extends in the first direction. The first conductive layer includes a region that overlaps in the second direction a region where extension lines of the first and second insulating layers intersect, and the third conductive layer does not overlap this intersection region in the second direction.Type: GrantFiled: August 27, 2018Date of Patent: July 20, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kosei Noda, Takeshi Murata, Mitsuhiko Noda
-
Patent number: 11063003Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor wafer, a plurality of semiconductor chips, and a plurality of first protection dams. The semiconductor wafer has a plurality of functional regions separated by a plurality of vertical streets and a plurality of horizontal streets. The semiconductor chips are mounted on the functional regions, respectively. The first protection dams are disposed on the vertical streets and the horizontal streets and spaced from the semiconductor chips. A height of the first protection dam is not less than a height of the semiconductor chip.Type: GrantFiled: October 2, 2018Date of Patent: July 13, 2021Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Ching-Hung Chang, Hsih-Yang Chiu
-
Patent number: 11056575Abstract: A method for manufacturing a power semiconductor device includes forming a drift region in a substrate, forming a trench in the drift region, forming a gate insulating layer in the trench, depositing a conductive material on the substrate, forming a gate electrode in the trench, forming a body region in the substrate, forming a highly doped source region in the body region, forming an insulating layer that covers the gate electrode, etching the insulating layer to open the body region, implanting a dopant into a portion of the body region to form a highly doped body contact region, so that the highly doped source region and the highly doped body contact region are alternately formed in the body region; and forming a source electrode on the highly doped body contact region and the highly doped source region.Type: GrantFiled: October 23, 2017Date of Patent: July 6, 2021Assignee: MagnaChip Semiconductor, Ltd.Inventors: Soo Chang Kang, Seong Jo Hong
-
Patent number: 11056420Abstract: The present invention relates generally to a pressing-type semiconductor power device package, and more specifically to a pressing-type semiconductor power device package in which a semiconductor chip, such as a transistor or diode, is formed into a package via a pressing structure without using any conductive adhesive, such as solder, which is used in the past, thereby improving production efficiency and durability.Type: GrantFiled: December 20, 2018Date of Patent: July 6, 2021Assignee: JMJ KOREA CO., LTD.Inventors: Yunhwa Choi, Jeonghun Cho, Jungtae Cho
-
Patent number: 11049869Abstract: A MONOS transistor as a first transistor can have improved reliability and a change in channel-width dependence of the property of a second transistor can be suppressed. The semiconductor device according to one embodiment includes a semiconductor substrate having first and second regions on the first main surface, an insulating film on the second region, a semiconductor layer on the insulating film, a memory transistor region in the first region, a first transistor region in the second main surface of the semiconductor layer, a first element isolation film surrounding the memory transistor region, and a second element isolation film surrounding the first transistor region. A first recess depth between the bottom of the first recess and the first main surface in the memory transistor region is larger than a second recess depth between the bottom of a second recess and the second main surface in the first transistor region.Type: GrantFiled: February 19, 2019Date of Patent: June 29, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hideaki Yamakoshi, Shinichiro Abe, Takashi Hashimoto, Yuto Omizu