Patents Examined by Thao X. Le
  • Patent number: 10811068
    Abstract: Varying energy barriers of magnetic tunnel junctions (MTJs) in different magneto-resistive random access memory (MRAM) arrays in a semiconductor die to facilitate use of MRAM for different memory applications is disclosed. In one aspect, energy barriers of MTJs in different MRAM arrays are varied. The energy barrier of an MTJ affects its write performance as the amount of switching current required to switch the magnetic orientation of a free layer of the MTJ is a function of its energy barrier. Thus, by varying the energy barriers of the MTJs in different MRAM arrays in a semiconductor die, different MRAM arrays may be used for different types of memory provided in the semiconductor die while still achieving distinct performance specifications. The energy barrier of an MTJ can be varied by varying the materials, heights, widths, and/or other characteristics of MTJ stacks.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Xia Li, Wei-Chuan Chen, Wah Nam Hsu, Seung Hyuk Kang
  • Patent number: 10801710
    Abstract: An LED lighting device capable of discharging heat generated from a light emitting element to the outside the LED lighting device. An LED lighting device includes: a plurality of light emitting elements; a mounted substrate on which the light emitting elements are mounted; and an electrode portion configured to supply a current to the light emitting elements from outside the LED lighting device. On the mounted substrate, a wiring substrate is located. On the upper surface of the mounted substrate, the mounted substrate includes: a light emitting region in which the plurality of light emitting elements are mounted; an exposed region which is located on the outer side of the light emitting region and through which the upper surface of the mounted substrate is exposed; and a wiring region which is located on the outer side of the light emitting region and in which the wiring substrate is located.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 13, 2020
    Assignees: CITIZEN ELECTRONICS CO., LTD., CITIZEN WATCH CO., LTD.
    Inventors: Takashi Iino, Sadato Imai
  • Patent number: 10804288
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: October 13, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinya Arai
  • Patent number: 10804320
    Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a substrate including a cell region and a peripheral region, a magnetic tunnel junction pattern on the cell region, a capping insulation layer covering a sidewall of the magnetic tunnel junction pattern, and an upper insulation layer including a first portion on the capping insulation layer and a second portion on the peripheral region. A level of a bottom surface of the second portion is lower than that of a bottom surface of the capping insulation layer.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonsung Han, Seung Pil Ko
  • Patent number: 10790410
    Abstract: An optoelectronic device configured for improved light extraction through a region of the device other than the substrate is described. A group III nitride semiconductor layer of a first polarity is located on the substrate and an active region can be located on the group III nitride semiconductor layer. A group III nitride semiconductor layer of a second polarity, different from the first polarity, can located adjacent to the active region. A first contact can directly contact the group III nitride semiconductor layer of the first polarity and a second contact can directly contact the group III nitride semiconductor layer of the second polarity. Each of the first and second contacts can include a plurality of openings extending entirely there through and the first and second contacts can form a photonic crystal structure. Some or all of the group III nitride semiconductor layers can be located in nanostructures.
    Type: Grant
    Filed: October 23, 2016
    Date of Patent: September 29, 2020
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Grigory Simin, Alexander Dobrinsky
  • Patent number: 10763372
    Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 1, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takeshi Osada, Shunpei Yamazaki
  • Patent number: 10748973
    Abstract: A display device includes a display panel including a lower surface, an upper surface facing the lower surface, and a first area, a first film positioned below the lower surface and provided with a film groove defined therein overlapping with the first area, a second film disposed on the upper surface, and an adhesive layer disposed between the lower surface of the display panel and the first film and provided with an adhesive groove defined therein overlapping with the first area. The first area extends across the display panel along a first direction, one side surface of the adhesive groove is defined by one line when viewed in a cross section taken along a second direction crossing the first direction, and one side surface of the film groove is defined by two or more lines when viewed in the cross section taken along the second direction.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Junghoon Han, Jihoon Kim, Daeseung Mun
  • Patent number: 10741797
    Abstract: An OLED display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to transfer a scan signal, a data line and a driving voltage line crossing the scan line and respectively configured to transfer a data voltage and a driving voltage, and a switching transistor electrically connected to the scan line and the data line and including a switching drain electrode configured to output the data voltage. The display also includes a driving transistor including a driving gate electrode, a driving drain electrode, and a driving source electrode electrically connected to the switching drain electrode. The display further includes a storage capacitor including a first storage electrode electrically connected to the driving gate electrode and a second storage electrode formed on the same layer as the driving voltage line.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Myoung Geun Cha, Jin Goo Jung, Yoon Ho Khang, Se Mi Kim
  • Patent number: 10741636
    Abstract: A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. The substrate has a first blind hole and a trench. The first blind hole communicates with the trench. The first blind hole has a first depth, and the trench has a second depth smaller than the first depth. The capacitor structure includes a first inner conductor, a first inner insulator, and an outer conductor. The first inner conductor is in the first blind hole. The first inner insulator surrounds the first inner conductor. The outer conductor has a first portion surrounding the first inner insulator and an extending portion extending from the first portion. The first portion is in the first blind hole, and the extending portion is in the trench. The first inner conductor is separated from the outer conductor by the first inner insulator.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tieh-Chiang Wu
  • Patent number: 10734531
    Abstract: A device and method for manufacturing a two-dimensional electrostrictive field effect transistor having a substrate, a source, a drain, and a channel disposed between the source and the drain. The channel is a two-dimensional layered material and a gate proximate the channel. The gate has a column of an electrostrictive or piezoelectric or ferroelectric material, wherein an electrical input to the gate produces an elongation of the column that applies a force or mechanical stress on the channel and reduces a bandgap of two-dimensional material such that the two-dimensional electrostrictive field effect transistor operates with a subthreshold slope that is less than 60 mV/decade.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: August 4, 2020
    Assignee: The Penn State Research Foundation
    Inventor: Saptarshi Das
  • Patent number: 10727450
    Abstract: A display apparatus includes a flexible substrate, a thin-film transistor unit, and a light-emitting unit. The flexible substrate includes a display area has a first area, a peripheral area which is adjacent to the display area, and a first penetrating portion corresponding to the first area. The thin-film transistor unit is in the display area and at least a portion of the peripheral area. The thin-film transistor unit includes a thin-film transistor and an insulation layer and has a second penetrating portion at a location corresponding to the first penetrating portion. The light-emitting unit is on the thin-film transistor unit and includes a pixel electrode, an intermediate layer including an emission layer, and a counter electrode.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jonghyun Yun, Junyoung Kim, Seunggyu Tae, Jongmoo Huh, Kwangsoo Lee, Sangcheon Han
  • Patent number: 10714403
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a carrier, a first patterned conductive layer, an interconnection structure, a first semiconductor device, an encapsulant, a second patterned conductive layer, and a passivation layer. The carrier has a first surface and a second surface opposite to the first surface. The first patterned conductive layer is adjacent to the first surface of the carrier. The interconnection structure is disposed on the first patterned conductive layer and electrically connected to the first patterned conductive layer. The first semiconductor device is disposed on the interconnection structure and electrically connected to the interconnection structure. The encapsulant is disposed on the first patterned conductive layer and encapsulates the semiconductor device and the interconnection structure.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 14, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10665674
    Abstract: A method for manufacturing a semiconductor device is described that comprises providing a substrate, forming a plurality of fins having a first semiconductor material, replacing a first portion of at least one of the fins with a second semiconductor material, and distributing the second semiconductor material from the first portion to a second portion of the at least one of the fins.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yi-Jing Lee, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 10665714
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a semiconductor substrate. In the method, at least two spacer layers are formed around a first fin of the plurality of fins, and a single spacer layer is formed around a second fin of the plurality of fins. The at least two spacer layers include a first spacer layer including a first material and a second spacer layer including a second material different from the first material. The single spacer layer includes the second material. The method also includes selectively removing part of the first spacer layer to expose part of the first fin, and epitaxially growing a source/drain region around the exposed part of the first fin.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 26, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juntao Li, Kangguo Cheng, ChoongHyun Lee, Shogo Mochizuki
  • Patent number: 10658520
    Abstract: A semiconductor device including a transistor having low leakage current between the drain and the gate is provided. The semiconductor device includes an insulating film provided so as to cover a corner of the first conductor and a second conductor provided so as to overlap with a corner of the first conductor with the insulating film provided therebetween. Variation in the thickness of the insulating film can be prevented by making the first conductor have a rounded corner. Furthermore, concentration of electric field due to the corner of the first conductor can be relaxed. Thus, the current leakage between the first conductor and the second conductor can be reduced.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: May 19, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Yoshinori Ieda
  • Patent number: 10658558
    Abstract: A light-emitting device is disclosed, including: a substrate; a light-emitting diode (LED) formed on a first surface of the substrate, the LED being arranged to emit primary light; a fence disposed on a second surface of the substrate, the fence including a plurality of walls arranged to define a cell; a light-converting structure disposed in the cell, the light-converting structure being arranged to convert at least a portion of the primary light to secondary light having a wavelength that is different from the wavelength of the primary light; and a reflective element formed on one or more outer surfaces of the walls of the fence, such that the reflective element and the light-converting structure are disposed on opposite sides of the walls of the fence.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: May 19, 2020
    Assignee: Lumileds LLC
    Inventors: Brendan Moran, Lex Kosowsky
  • Patent number: 10658436
    Abstract: An organic light emitting display device according to an exemplary embodiment of the present disclosure includes a flexible substrate, an adhesive layer, a pad unit, and a module. The flexible substrate includes a display area in which a display unit is disposed, a first non-display area which encloses the display area, a bending area which extends from the first non-display area, and a second non-display area which extends from one side of the bending area. The adhesive layer is disposed on the display unit. The pad unit is disposed in the second non-display area of the flexible substrate. The module is connected to be in contact with the pad unit. In this case, the adhesive layer extends from the display area to the bending area to cover at least a part of the bending area of the flexible substrate.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 19, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: HoWon Shin, Soyeon Jo
  • Patent number: 10658375
    Abstract: A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Gukhyon Yon, Dongwoo Kim, Kihyun Hwang, Dongkyum Kim, Dongchul Yoo
  • Patent number: 10658595
    Abstract: An organic light emitting diode includes: a first electrode; a second electrode facing the first electrode; a light emission layer between the first electrode and the second electrode; an electron injection layer between the second electrode and the light emission layer; and a buffer layer between the electron injection layer and the second electrode, where the electron injection layer includes a dipolar material and a first metal, and the buffer layer includes a metal having a work function of 4.0 eV or less.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: May 19, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seok Gyu Yoon, Dong Chan Kim, Eung Do Kim, Bo Ra Jung, Kyu Hwan Hwang, Sung Chul Kim, Won-Jong Kim, Young-Woo Song, Jong Hyuk Lee
  • Patent number: 10651264
    Abstract: A display device may includes: a substrate including a pixel area and a peripheral area; pixels provided in the pixel area of the substrate, each of the pixels including a light-emitting element provided with a pixel electrode; scan lines and data lines coupled to the pixels; a power line configured to supply driving power to the light-emitting elements, and extending in one direction; and an initialization power line configured to supply initialization power to the light-emitting elements. The power line and the initialization power line may be provided on different layers. The initialization power line may include: first conductive lines extending in a direction oblique to the scan lines and the data lines; and conductive lines intersecting the first conductive lines. The first and second conductive lines may be disposed in areas between the pixel electrodes of adjacent light-emitting elements.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Yong An, Yun Kyeong In, Jun Won Choi, Won Mi Hwang