Patents Examined by Thien F Tran
  • Patent number: 10381554
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a magnetic tunnel junction. The magnetic tunnel junction includes a fixed layer structure, a free layer structure, and a barrier layer disposed between the fixed layer structure and the free layer structure. The fixed layer structure includes a first magnetic layer and a second magnetic layer that is disposed between the first magnetic layer and the barrier layer. The first magnetic layer is configured to produce a first magnetic moment that substantially correlates to a second magnetic moment of the second magnetic layer as a function of temperature.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Vinayak Bharat Naik, Kazutaka Yamane, Seungmo Noh, Kangho Lee, Dimitri Houssameddine, Taiebeh Tahmasebi, Chenchen Jacob Wang
  • Patent number: 10381219
    Abstract: Methods for forming a silicon nitride film by a plasma enhanced atomic layer deposition (PEALD) process are provided. The methods may include: providing a substrate into a reaction chamber; and performing at least one unit deposition cycle of a PEALD process, wherein a unit cycle comprises, contacting the substrate with a vapor phase reactant comprising a silicon precursor; and contacting the substrate with a reactive species generated from a gas mixture comprising a nitrogen precursor and an additional gas. Methods for improving the etch characteristics of a silicon nitride film utilizing a post deposition plasma treatment are also provided.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 13, 2019
    Assignee: ASM IP Holding B.V.
    Inventors: Shinya Ueda, Tomomi Takayama, Taishi Ebisudani, Toshiya Suzuki, Tomohiro Kubota
  • Patent number: 10374195
    Abstract: An adhesive film and an organic electronic device including the same are provided. The adhesive film includes: a first bonding layer including a first bonding component layer, a moisture absorbent, and first core shell particles; and a second bonding layer disposed below the first bonding layer and including second core shell particles, which are formed of a different material from the first core shell particles, wherein each of the first core shell particles includes a first shell and a first core surrounded by the first shell and each of the second core shell particles includes a second shell and a second core surrounded by the second shell.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 6, 2019
    Assignee: SHINWHA INTERTEK CORP
    Inventors: Sung Chul Yoon, Cheol Heung Ahn, Hwi Yong Lee, Ji Woong Park, Dong Hyun Kim, Geoung Min Shin
  • Patent number: 10373881
    Abstract: A system for analyzing defects comprises determining coordinates of a defect using a wafer inspection tool; identifying a structure of interest near the defect coordinates; directing a focused ion beam toward the wafer to expose the structure of interest; and forming an image of the exposed structure of interest, wherein the focused ion beam is directed to the mill at a location corresponding to the identified structure of interest rather than at the coordinates of the defect.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 6, 2019
    Assignee: FEI Company
    Inventor: Thomas G. Miller
  • Patent number: 10373864
    Abstract: Methods of wetting a semiconductor substrate may include forming a controlled atmosphere in a processing chamber housing the semiconductor substrate. The semiconductor substrate may define a plurality of features, which may include vias. The methods may include flowing a wetting agent into the processing chamber. A chamber pressure may be maintained below about 100 kPa. The methods may also include wetting the plurality of features defined in the substrate.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: August 6, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Paul McHugh, Bridger Hoerner, Marvin Bernt, Thomas H. Oberlitner, Brian Aegerter, Richard W. Plavidal, Andrew Anten, Adam McClure, Randy Harris
  • Patent number: 10361184
    Abstract: A semiconductor device according to an embodiment includes: an insulating film formed on a voltage supporting region B; an overvoltage protection diode that includes an n-type semiconductor layer and a p-type semiconductor layer; conductor portions that are formed on the insulating film and are electrically connected to the overvoltage protection diode; and a high-potential portion arranged above the overvoltage protection diode via an insulating film. The p-type impurity concentration of the p-type semiconductor layer is lower than the n-type impurity concentration of the n-type semiconductor layer. In the reverse bias application state, the high-potential portion has a higher potential than a potential of the potential of the p-type semiconductor layer disposed directly under the high-potential portion.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 23, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Ryohei Kotani, Toshiki Matsubara, Nobutaka Ishizuka, Masato Mikawa, Hiroshi Oshino
  • Patent number: 10361095
    Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: July 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abbas Ali, Dhishan Kande, Qi-Zhong Hong, Young-Joon Park, Kyle McPherson
  • Patent number: 10345660
    Abstract: Disclosed is a manufacturing method of a photo spacer structure of an array substrate, including: forming first pad carriers and second pad carriers having height difference; depositing black photosensitive resin material to cover the first pad carriers and the second pad carriers; implementing exposure to the black photosensitive resin material through a mask, having light transmitting areas and light shielding areas, and light transmission adjusting parts are arranged corresponding to the second pad carriers, and implementing development to form main photo spacers on the first pad carriers, sub photo spacers on the second pad carriers and grooves or trenches in areas around the sub photo spacer with the light transmission adjusting parts; implementing a high-temperature baking and leveling treatment to the black photosensitive resin material to level and fill at least a portion of the resin material of the sub photo spacers to the grooves or the trenches.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 9, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Wu Cao
  • Patent number: 10347604
    Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: July 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuki Yagyu, Seiya Isozaki
  • Patent number: 10340207
    Abstract: According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 2, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Imori, Kenji Yamada
  • Patent number: 10340136
    Abstract: A method for defining thin film layers on a surface of a substrate includes exposing the surface of the substrate to a first precursor via a first plasma to allow the first precursor to be absorbed by the surface of the substrate. A second precursor that is different from the first precursor is applied to the surface of the substrate via a second plasma. The second precursor is a Carbon dioxide precursor that releases sufficient oxygen radicals to react with the first precursor to form an oxide film layer on the surface of the substrate.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: July 2, 2019
    Assignee: Lam Research Corporation
    Inventors: Douglas Walter Agnew, Ishtak Karim
  • Patent number: 10325949
    Abstract: An image sensor device is provided. The image sensor device includes a substrate having a first surface, a second surface, and a light-sensing region. The image sensor device includes a first isolation structure in the substrate and adjacent to the first surface. The first isolation structure surrounds the light-sensing region. The image sensor device includes a second isolation structure passing through the first isolation structure and the substrate under the first isolation structure. The second isolation structure surrounds the light-sensing region and a portion of the first isolation structure.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chao-Ching Chang, Sheng-Chan Li, Cheng-Hsien Chou, Tsung-Wei Huang, Min-Hui Lin, Yi-Ming Lin
  • Patent number: 10312099
    Abstract: A wafer processing method includes a protective film providing step of providing a protective film on the front side of a wafer, a wafer unit forming step of applying a liquid resin curable by an external stimulus to the front side of the wafer and then curing the liquid resin by applying the external stimulus to form a protective member, thereby forming a wafer unit composed of the wafer, the protective film, and the protective member in the condition where the front side of the wafer is covered with the protective member, a grinding step of holding the protective member on a holding surface of a chuck table and then grinding the back side of the wafer of the wafer unit to thereby reduce the thickness of the wafer, and a peeling step of peeling the protective member and the protective film from the wafer reduced in thickness.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 4, 2019
    Assignee: Disco Corporation
    Inventors: Kazuma Sekiya, Karl Heinz Priewasser
  • Patent number: 10312153
    Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: June 4, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungin Choi, Ah-Young Cheon, Kwang-Yong Yang, Myungil Kang, Dohyoung Kim, YoonHae Kim
  • Patent number: 10302989
    Abstract: Disclosed is a method for improving transmittance of flat or curved liquid crystal display panel. The method includes the following steps. (1) A substrate is manufactured according to the BPS technology. The substrate includes an array substrate and a CF substrate. A spacer and a black matrix are provided on a side of the array substrate and a transparent conductive electrode film is provided on a side of the CF substrate. (2) Marks are engraved on designated positions of the CF substrate by means of a laser and the CF substrate is aligned with the marks on a platform of a UV2A exposure machine. (3) Tracking lines are engraved on the transparent conductive electrode film and a region bounded by the tracking lines is aligned with a light-shielding region of a gate line or a light-shielding region of a data line on the side of the array substrate. (4) The substrate is exposed to light and a mask is used to track the tracking lines.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: May 28, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Yanjun Song, Xiang Li, Chung Ching Hsieh, Chung Yi Chiu
  • Patent number: 10305036
    Abstract: A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Mattia Boniardi, Andrea Redaelli
  • Patent number: 10304698
    Abstract: A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: May 28, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Tae Ho Yoon, Yang Gyoo Jung, Min Ho Kim, Youn Seok Song, Dong Soo Ryu, Choong Hoe Kim
  • Patent number: 10304758
    Abstract: Techniques for forming a wafer level package device are disclosed. In one or more embodiments, the techniques include forming a wafer level lead frame on a carrier wafer and electrically connecting the wafer level lead frame to an active semiconductor wafer. The carrier wafer and the active semiconductor wafer have at least substantially the same coefficients of thermal expansion. The carrier wafer can be removed from the wafer level package device, and a number of connectors can be formed on the wafer level package device. The wafer level package device can be singulated to form chip packages, such as DFN or QFN packages.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: May 28, 2019
    Assignee: MAXIM INTEGRATED PRODUCTS, INC
    Inventors: Karthik Thambidurai, Ahmad Ashrafzadeh, Viresh P. Patel, Viren Khandekar
  • Patent number: 10297710
    Abstract: A method of processing a wafer includes applying a laser beam having a wavelength that is transmittable through a sapphire substrate to the wafer while positioning a focused spot of the beam within the wafer in regions corresponding to projected dicing lines through a reverse side of the wafer, thereby forming a plurality of shield tunnels made up of a plurality of pores and an amorphous body surrounding the pores, at predetermined spaced intervals in the wafer along the projected dicing lines. A laser beam having a wavelength that is transmittable through the sapphire substrate to the wafer is applied while positioning a focused spot of the laser beam within the wafer in the projected dicing lines through the reverse side of the wafer, thereby forming modified layers between adjacent shield tunnels. Exerting external forces to the wafer divides the wafer into a plurality of optical device chips.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: May 21, 2019
    Assignee: Disco Corporation
    Inventor: Naotoshi Kirihara
  • Patent number: 10297644
    Abstract: An OLED display device includes a substrate including red, green, and blue pixel areas, a first electrode at each of the red pixel area, the green pixel area, and the blue pixel area on the substrate, a hole transport layer on the first electrode, a light emission portion on the hole transport layer, the light emission portion including a red light emitting layer at the red pixel area, a green light emitting layer at the green pixel area, and a blue light emitting layer at the blue pixel area, a first charge generation layer and a first resonance auxiliary layer between the hole transport layer and the blue light emitting layer, a second resonance auxiliary layer between the hole transport layer and the red light emitting layer, an electron transport layer on the light emission portion, and a second electrode on the electron transport layer.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: May 21, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hajin Song, Byeongwook Yoo, Jihwan Yoon, Jaehoon Hwang