Patents Examined by Thien F Tran
  • Patent number: 10978337
    Abstract: Aluminum-containing layers and systems and methods for forming the same are provided. In an embodiment, a method includes depositing an aluminum-containing layer on a substrate in a chamber by atomic layer deposition. The depositing further includes contacting the substrate with an aluminum-containing precursor in a first pulse having a first peak pulse flow rate and a first pulse width; contacting the substrate with a nitrogen-containing precursor; contacting the substrate with the aluminum-containing precursor in a second pulse having a second peak pulse flow rate and a second pulse width; and contacting the substrate with the nitrogen-containing precursor. The first peak pulse flow rate is greater than the second peak pulse flow rate. The first pulse width is smaller than the second pulse width.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jyh-nan Lin, Mu-Min Hung, Kai-Shiung Hsu, Ding-I Liu
  • Patent number: 10978585
    Abstract: A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; an active region comprising: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body; and an active region contact electrode disposed within the active region contact trench; and an island region under the active region contact trench and disconnected from the body, the island region having an opposite polarity as the epitaxial layer; wherein the active region contact trench has a non-uniform depth.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Inventors: Anup Bhalla, Xiaobin Wang, Ji Pan, Sung-Po Wei
  • Patent number: 10971597
    Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer includes a first section and a second section that are located over the active region. An emitter is positioned on the first section of the base layer, and an extrinsic base layer is positioned on the second section of the base layer. The extrinsic base layer has a side surface adjacent to the emitter. The side surface of the extrinsic base layer is inclined relative to a top surface of the base layer in a direction away from the emitter.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Qizhi Liu, Vibhor Jain, John J. Pekarik
  • Patent number: 10964703
    Abstract: A method for fabricating a semiconductor device is provided. The method includes the actions of: providing a substrate comprising a preliminary pattern formed thereon; forming an opening through the preliminary pattern to expose an etch stop layer in the preliminary pattern; forming a dielectric layer on a sidewall of the opening; performing a first etching process to penetrate the etching stop layer and form a hole; performing a second etching process to expand a portion of the hole in the substrate; removing the dielectric layer; and depositing a conductive preliminary pattern on the sidewall of the opening and in the hole.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 30, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Chang-Hyeon Nam, Injoon Yeo
  • Patent number: 10964809
    Abstract: A semiconductor device comprises: a cell region that includes a semiconductor element; an outer peripheral region that surrounds an outer periphery of the cell region; a substrate that has a front surface and a back surface, and is made of a semiconductor of a first or second conductivity type; a first conductivity layer that is formed on the front surface of the substrate and made of the semiconductor of the first conductivity type having a lower impurity concentration than impurity concentration of the substrate; a first electrode that is provided on an opposite side of the substrate across the first conductivity layer, the first electrode being provided in the semiconductor element; and a second electrode that is placed toward the back surface of the substrate, the second electrode being provided in the semiconductor element.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: March 30, 2021
    Assignee: DENSO CORPORATION
    Inventors: Masato Noborio, Masayasu Ishiko, Jun Saito
  • Patent number: 10957752
    Abstract: In a method of manufacturing a transparent display device, a substrate including a pixel region and a transmission region may be provided. A first electrode may be formed on the substrate in the pixel region, and a display layer may be formed on the first electrode. A second electrode facing the first electrode may be formed on the display layer, and a capping structure including a first capping layer and a second capping layer may be formed on the second electrode. The first capping layer may be formed on the second electrode in the pixel region and a first region of the transmission region by using a mask that has an opening, the mask may be shifted, and the second capping layer may be formed on the second electrode in the pixel region and a second region of the transmission region by using the shifted mask.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: March 23, 2021
    Inventors: Jin-Koo Chung, Jeong-Woo Moon, Byoung-Hee Park, Jun-Ho Choi
  • Patent number: 10957532
    Abstract: Methods and apparatus for forming a conformal SiOC film on a surface are described. A SiCN film is formed on a substrate surface and exposed to a steam annealing process to decrease the nitrogen content, increase the oxygen content and leave the carbon content about the same. The annealed film has one or more of the wet etch rate or dielectric constant of the film.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 23, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ning Li, Zhelin Sun, Mihaela Balseanu, Li-Qun Xia, Bhaskar Jyoti Bhuyan, Mark Saly
  • Patent number: 10950631
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor wafer. The semiconductor wafer comprises a handle wafer. A first oxide layer is disposed over the handle wafer. A device layer is disposed over the first oxide layer. A second oxide layer is disposed between the first oxide layer and the device layer, wherein the first oxide layer has a first etch rate for an etch process and the second oxide layer has a second etch rate for the etch process, and wherein the second etch rate is greater than the first etch rate.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Liang Liu, Yeur-Luen Tu
  • Patent number: 10950640
    Abstract: An image sensor includes a plurality of pixels, at least one of the pixels comprising: a photodiode configured to generate charges in response to light; and a pixel circuit disposed on the substrate, and including a storage transistor configured to store the charges generated by the photodiode, and a transfer transistor connected between the storage transistor and a floating diffusion node, wherein a potential of a boundary region between the storage transistor and the transfer transistor has a first potential when the transfer transistor is in a turned-off state, and has a second potential, lower than the first potential, when the transfer transistor is in a turned-on state.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Gu Jin, Yong Hun Kwon, Young Chan Kim, Sae Young Kim, Sung Young Seo, Moo Sup Lim, Tae Sub Jung, Sung Ho Choi
  • Patent number: 10940611
    Abstract: A cleaving system employs a shaper, a positioner, an internal preparation system, an external preparation system, a cleaver, and a cropper to cleave a workpiece into cleaved pieces. The shaper shapes a workpiece into a defined geometric shape. The positioner then positions the workpiece such that the internal preparation system can generate a separation layer at the cleaving plane. The internal preparation system focuses a laser beam internal to the workpiece at a focal point and scans the focal point across the cleaving plane to create the separation layer. The external preparation system scores the external surface of the workpiece at a location coincident with the separation layer. The cleaver cleaves the workpiece by propagating the crack on the external surface along the separation layer. The cropper shapes the cleaved piece into a geometric shape as needed.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: March 9, 2021
    Assignee: HALO INDUSTRIES, INC.
    Inventors: Andrei Teodor Iancu, Charles William Rudy
  • Patent number: 10943994
    Abstract: A manufacturing method for a shielded gate trench device comprises the following steps: Step 1, forming a gate trench in a first epitaxial layer; Step 2, forming a first dielectric layer and fully filling the gate trench with a first polysilicon layer; Step 3, forming a top trench: Step 31, carrying out primary polysilicon dry-etching; Step 32, carrying out primary dielectric layer wet-etching to decrease the thickness of the first dielectric layer in the top trench; Step 33, carrying out secondary polysilicon dry-etching; Step 34, carrying out secondary dielectric layer wet-etching to remove the rest of the first dielectric layer on a side face of the top trench and to form the top trench; and Step 4, forming a trench gate in the top trench. By adoption of the manufacturing method, the gate-source capacitance and the gate-drain capacitance can be decreased, and thus, the input capacitance is decreased.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: March 9, 2021
    Assignee: Shanhai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Yulong Yang, Zhengrong Chen, Haofeng Shen
  • Patent number: 10942410
    Abstract: A display device includes a bottom substrate including a display area and a non-display area around the display area, a thin film transistor region in the display area, the thin film transistor region including a plurality of thin film transistors and a plurality of pixel electrodes each electrically connected to a respective one of the thin film transistors, a top substrate facing the bottom substrate with the thin film transistor region therebetween, a seal in the non-display area to surround the thin film transistor region, the seal being configured to bond the bottom substrate to the top substrate, a wiring group between the seal and the bottom substrate, the wiring group including a plurality of conductive lines spaced apart from each other by a predetermined interval, and a light-scattering layer between the seal and the top substrate, the light-scattering layer including light-scattering particles.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 9, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Donghee Shin, Yoomi Ra, Hyungjin Song, Soohong Cheon
  • Patent number: 10943880
    Abstract: Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 9, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Priyal Shah, Milind S. Bhagavat, Lei Fu
  • Patent number: 10937884
    Abstract: A semiconductor device structure includes a gate stack and an adjacent source/drain contact structure formed over a semiconductor substrate. The semiconductor device structure includes a first gate spacer structure extending from a sidewall of the gate stack to a sidewall of the source/drain contact structure, and a second gate spacer structure formed over the first gate spacer structure and between the gate stack and the source/drain contact structure. The second gate spacer structure includes first and second gate spacer layers adjacent to the sidewall of the gate stack and the sidewall of the source/drain contact structure, respectively, and a third gate spacer layer separating the first gate spacer layer from the second gate spacer layer, so that an air gap is sealed by the first, second, and the third gate spacer layers and the first gate spacer structure.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Tsung Wang, Lin-Yu Huang, Chia-Lin Chuang, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 10937899
    Abstract: A semiconductor device include a semiconductor substrate, a first trench electrode formed in the semiconductor substrate and having a first portion, a second trench electrode formed in the semiconductor substrate having a second portion facing the first portion, a floating layer of a first conductivity type formed around the first and second trench electrodes, a drift layer of a second conductivity type connected to the floating layer of the first conductivity type and formed between the first and second trench electrodes, an impurity layer of the first conductivity type connected to the drift layer of the second conductivity type and formed between the first and second trench electrodes, and a floating layer control gate having a portion located at least above the impurity layer of the first conductivity type.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: March 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nao Nagata
  • Patent number: 10930568
    Abstract: A semiconductor structure includes at least one non-self-aligned contact in a metallization layer and a fabrication method for forming the same are disclosed. The method includes forming gate metal in a gate stack on a substrate and forming a source-drain contact in a source-drain stack on the substrate. The gate stack and the source-drain stack are separated by a sidewall spacer. The method recesses the sidewall spacer thereby forming a trench. In the trench, a first outer metal liner and a second outer metal liner are recessed, horizontally enlarging the trench to form a widened trench over respective top surfaces of the recessed first outer metal liner, second outer metal liner, and sidewall spacer. The method then deposits dielectric material filling the widened trench and contacting the first inner metal core, the second inner metal core, the first outer metal liner, the second outer metal liner, and the sidewall spacer.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Kangguo Cheng, Chanro Park, Juntao Li
  • Patent number: 10930748
    Abstract: A semiconductor device includes: a semiconductor (10 ?m?tsi?30 ?m); a metal layer (30 ?m?tag?60 ?m) comprising Ag; a metal layer (10 ?m?tni?35 ?m) comprising Ni; and transistors. The transistors include a source electrode and a gate electrode on the semiconductor layer. The metal layer functions as a common drain region for the transistors. The ratio of the lengths of the longer side and the shorter side of the semiconductor layer is at most 1.73. The ratio of the surface area and the perimeter length of each electrode included in the source electrode is at most 0.127. The cumulative surface area of the source electrode and the gate electrode is at most 2.61 mm2. The length of the shorter side of the source electrode is at most 0.3 mm, and 702<2.33×tsi+10.5×tag+8.90×tni<943 is satisfied.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 23, 2021
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Masao Hamasaki, Masaaki Hirako, Ryosuke Okawa, Ryou Kato
  • Patent number: 10910478
    Abstract: A MOSFET device includes an epitaxial region disposed on an upper surface of a substrate, and at least two body regions formed in the epitaxial region. The body regions are disposed proximate an upper surface of the epitaxial region and spaced laterally apart. The device further includes at least two source regions disposed in respective body regions, proximate an upper surface of the body regions, and a gate structure including at least two planar gates and a trench gate. Each of the planar gates is disposed on the upper surface of the epitaxial region and overlaps at least a portion of a corresponding body region. The trench gate is formed partially through the epitaxial region and between the body regions. A drain contact disposed on a back surface of the substrate provides electrical connection with the substrate.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: February 2, 2021
    Inventor: Shuming Xu
  • Patent number: 10908321
    Abstract: A glass laminate includes a glass substrate including a first main surface and a second main surface, and a functional layer at least on the first main surface. The functional layer includes at least two layers having a refractive index different from each other and the at least two layers are alternately laminated. The functional layer includes an outermost layer farthest from the glass substrate and a second layer that is adjacent to the outermost layer and lies closer to the glass substrate than the outermost layer. The outermost layer includes SiO2 as a main component. The second layer has a carbon concentration of 3×1018 atoms/cm3 or more and 5×1019 atoms/cm3 or less, and the carbon concentration of the second layer is lower than that of the outermost layer.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: February 2, 2021
    Assignee: AGC Inc.
    Inventors: Kensuke Fujii, Michinori Suehara, Kazunari Tohyama
  • Patent number: 10903236
    Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kangyoon Choi, Dong-Sik Lee, Jongwon Kim, Gilsung Lee, Eunsuk Cho, Byungyong Choi, Sung-Min Hwang