Abstract: A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

Abstract: In some embodiments method comprises depositing a ferroelectric layer on a top surface of a semiconductor wafer and forming one or more gaps in the ferroelectric layer. The one or more gaps can be formed on a repetitive spacing to relieve stresses between the ferroelectric layer and the semiconductor wafer. A first dielectric layer is deposited over the ferroelectric layer and the first dielectric layer is planarized to fill in the gaps. A second dielectric layer is formed between the ferroelectric layer and the semiconductor wafer. The second dielectric layer can be formed by annealing the wafer in an oxidizing atmosphere such that an upper portion of the semiconductor substrate forms an oxide layer between the semiconductor substrate and the ferroelectric layer.

Abstract: A method for analyzing samples utilizing stable label isotope tracing includes receiving mass spectrometry (MS) data generated by an MS system performing untargeted data acquisition on a plurality of samples, performing untargeted feature extraction on the unlabeled compound data to generate a data set of first extracted features, generating a plurality of empirical molecular formulas respectively corresponding to the first extracted features, performing targeted isotopologue extraction on the labeled compound data to generate a data set of second extracted features, wherein the targeted isotopologue extraction is based on the empirical molecular formula and retention time of each first extracted feature, and identifying one or more groups of isotopologues from the second extracted features.

Abstract: Improving a reliability of a semiconductor device. A resistive element is comprised of a semiconductor layer of the SOI substrate and an epitaxial semiconductor layer formed on the semiconductor layer. The epitaxial semiconductor layer EP has two semiconductor portions formed on the semiconductor layer and spaced apart from each other. The semiconductor layer has a region on where one of the semiconductor portion is formed, a region on where another of the semiconductor portion is formed, and a region on where the epitaxial semiconductor layer is not formed.

Abstract: To suppress generation of flare and ghosts. A solid state image sensor includes: a pixel array configured to generate a pixel signal according to an amount of incident light by photoelectric conversion in units of pixels arranged in an array manner; a glass substrate bonded with a light-receiving surface of the pixel array; and a light-shielding film formed on a peripheral portion that is an outside of an effective pixel region of the pixel array, in which the light-shielding film is formed at a front stage of the glass substrate. The present disclosure can be adapted to an imaging device.

Abstract: Methods for removing an oxide film from a silicon-on-insulator structure are disclosed. The oxide may be stripped from a SOI structure before deposition of an epitaxial silicon thickening layer. The oxide film may be removed by dispensing an etching solution toward a center region of the SOI structure and dispensing an etching solution to an edge region of the structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor devices with a shared common backside well and methods of manufacture. The structure includes: adjacent gate structures over a semiconductor substrate; a common well in the semiconductor substrate under the adjacent gate structures; a deep trench isolation structure extending through the common well between the adjacent gate structures; and a shared diffusion region between the adjacent gate structures.

Abstract: A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N?1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes.

Abstract: A display device includes a substrate including a display area and a non-display area, a reference voltage supply line disposed in the non-display area and transmitting a reference voltage, and a driving voltage supply line disposed in the non-display area and transmitting a driving voltage. The reference voltage supply line includes a straight line part extending in a first direction and a curved line part extending from the straight line part to be bent, and the curved line part of the reference voltage supply line is disposed along a periphery of the display area.

Abstract: A method is provided to create lead compound(s) by discovering a general chemical structure, moieties, formula(s) to explore suitable compositions by computer simulation and/or robotic biological or biochemical experiments at least partially based upon employing said lead compound(s) discover method, which includes steps for inputting at least one chemical formula and at least one byproduct formula, steps for creating a list of dipeptides that might dissociate the byproduct from the input formula by way of catalysis, steps for using these dipeptides to fingerprint a protein from its peptide sequence, and searching a protein database or use experimental methods to search for such proteins. A composition creating means is provide by way of computer simulation and/or robotic biological or biochemical experiments at least partially based upon employing, as lead compound(s), the final chemical structure, moieties, formula(s) generated and communicated the above method.

Abstract: A structure includes a galvanic isolation including a horizontal portion including a first redistribution layer (RDL) electrode in a first insulator layer, and a second RDL electrode in the first insulator layer laterally spaced from the first RDL electrode. An isolation break includes a trench defined in the first insulator layer between the first RDL electrode and the second RDL electrode, and at least one second insulator layer in the trench. The first insulator layer and the second insulator layer(s) are between the first RDL electrode and the second RDL electrode. The isolation may separate, for example, voltage domains having different voltage levels. A related method is also disclosed. The isolation may also include a vertical portion using the first RDL electrode and another electrode in a metal layer separated from the first RDL electrode by a plurality of interconnect dielectric layers.

Abstract: A semiconductor FET (field effect transistor) including a plurality of nanosheet channels disposed between a first source/drain region and a second source/drain region and a common metal contact for the first source/drain region and the second source/drain region. The first source/drain region includes a p-type material; and the second source/drain region includes an n-type material.

Abstract: In radio-frequency (RF) devices integrated on semiconductor-on-insulator (e.g., silicon-based) substrates, RF losses may be reduced by increasing the resistivity of the semiconductor device layer in the vicinity of (e.g., underneath and/or in whole or in part surrounding) the metallization structures of the RF device, such as, e.g., transmission lines, contacts, or bonding pads. Increased resistivity can be achieved, e.g., by ion-implantation, or by patterning the device layer to create disconnected semiconductor islands.

Abstract: An approach for a nanosheet device with a single diffusion break is disclosed. The device comprises of active gate is formed above the BDI. At least the SDB is also formed over BDI with dielectric filled gate. The dielectric fill forms an indentation into the remaining nanosheets, under the spacer region, or between the inner spacers, in the SDB region. The method of creating the device comprises of, forming a gate cut opening between two ends of a dummy gate of one or more gates; forming a first sacrificial material on the gate cut opening; creating a single diffusion break; removing the dummy gate and oxide layer; removing, selectively a second sacrificial material; trimming, selectively stack of nanosheets; and forming dielectric in the gate cut opening and the single diffusion break.

Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

Abstract: In one embodiment, a semiconductor device includes a substrate, insulating films and first films alternately stacked on the substrate, at least one of the first films including an electrode layer and a charge storage layer provided on a face of the electrode layer via a first insulator, and a semiconductor layer provided on a face of the charge storage layer via a second insulator. The device further includes at least one of a first portion including nitrogen and provided between the first insulator and the charge storage layer with an air gap provided in the first insulator, a second portion including nitrogen, provided between the charge storage layer and the second insulator, and including a portion protruding toward the charge storage layer, and a third portion including nitrogen and provided between the second insulator and the semiconductor layer with an air gap provided in the first insulator.

Abstract: A processor implemented method of evaluating at least one potential tastant from a plurality of tastants is provided. The processor implemented method includes at least one of: receiving, information associated with a plurality of molecular activities; generating, a plurality of data-based models based on the known taste index associated with at least one tastant and information from associated molecular structure/descriptors; classifying, a new molecule based on the generated data-based models for the at least one tastant; screening, the one or more classified new molecules in an applicability domain of the generated data-based models based on the physics-based models by at least one molecular modeling technique; and evaluating, the at least one potential tastant from the screened molecules based on at least one of a bioavailability and a toxicity. In an embodiment, the plurality of molecular activities corresponds to a taste index and a binding energy.

Abstract: An IC structure includes first and second gates, first and second source/drain regions, and an isolation region. The first and second gates each have a first portion extending along a first direction and a second portion extending along a second direction. The first source/drain regions are respectively on opposite sides of the first portion of the first gate. The second source/drain regions are respectively on opposite sides of the first portion of the second gate. The isolation region has a lower portion between a first one of the first source/drain regions and a first one of the second source/drain regions, and an upper portion partially overlapping with the second portion of first gate and the second portion of the second gate. A width of the lower portion is a less than a width of the upper portion.

Abstract: A semiconductor device structure includes a silicon-on-insulator (SOI) region. The SOI region includes a semiconductor substrate, a buried oxide layer disposed over the semiconductor substrate, and a silicon layer disposed over the buried oxide layer. The semiconductor device structure also includes a first shallow trench isolation (STI) structure penetrating through the silicon layer and the buried oxide layer and extending into the semiconductor substrate. The first STI structure includes a first liner contacting the semiconductor substrate and the silicon layer, a second liner covering the first liner and contacting the buried oxide layer, and a third liner covering the second liner. The first liner, the second liner and the third liner are made of different materials. The first STI structure also includes a first trench filling layer disposed over the third liner and separated from the second liner by the third liner.