Patents Examined by Thinh T Nguyen
  • Patent number: 11574993
    Abstract: Embodiments disclosed herein include electronic packages with embedded magnetic materials and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, where the package substrate comprises a plurality of dielectric layers. In an embodiment a plurality of passive components is located in a first dielectric layer of the plurality of dielectric layers. In an embodiment, first passive components of the plurality of passive components each comprise a first magnetic material, and second passive components of the plurality of passive components each comprise a second magnetic material. In an embodiment, a composition of the first magnetic material is different than a composition of the second magnetic material.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Rengarajan Shanmugam, Suddhasattwa Nad, Darko Grujicic, Srinivas Pietambaram
  • Patent number: 11569267
    Abstract: A method for forming an integrated circuit includes following operations. A substrate having a first region, a second region and an isolation structure is received. A portion of the substrate is removed such that the second region is recessed. A portion of the isolation structure is removed to obtain a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed over the first top surface, the second top surface and the boundary. A dielectric structure is formed over the substrate. A top surface of the first device, a top surface of the second device and a top surface of the dummy structure are aligned with each other.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Te-An Chen
  • Patent number: 11569288
    Abstract: A semiconductor structure includes a sensor chip. The sensor chip includes a pixel array region, a bonding pad region, and a periphery region surrounding the pixel array region. The semiconductor structure further includes a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, and the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 11569289
    Abstract: A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 11569268
    Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: January 31, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Ryan Sporer, George R. Mulfinger, Yusheng Bian
  • Patent number: 11563193
    Abstract: The present invention provides a display device, including a display panel and an encapsulation cover disposed on the display panel. Two circles of border sealant are sequentially disposed at intervals between the bonding area of the encapsulation cover and the display panel from periphery to the inside. The invention provides a display device, which adopts a novel encapsulation structure so that it can effectively prevent external water and oxygen from invading into the internal display panel, and therefore improve its own stability.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: January 24, 2023
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Yang Miao
  • Patent number: 11562809
    Abstract: A method for automatically generating a universal set of stereoisomers of an organic molecule. The method includes: (1) segmenting an input molecule into a group of fragments; (2) matching the obtained isomer fragments with fragment templates in a fragment template library; (3) generating all isomers of the corresponding fragments according to fragment template information; and (4) traversing all the isomer fragments and sites thereof, and assembling the fragments at the two ends of a broken bond in the step (1) according to all possible sites of a broken-bond atom to obtain all stereoisomers; and if filtering is needed, performing filtering according to a specified filtering rule.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: January 24, 2023
    Assignee: SHENZHEN JINGTAI TECHNOLOGY CO., LTD.
    Inventors: Huanhuai Zhang, Guangxu Sun, Yang Liu, Shuhao Wen, Jian Ma, Lipeng Lai
  • Patent number: 11557654
    Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: January 17, 2023
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
  • Patent number: 11557717
    Abstract: A memory apparatus is provided which comprises: a stack comprising a magnetic insulating material and a transition metal dichalcogenide (TMD), wherein the magnetic insulating material has a first magnetization. The stack behaves as a free magnet. The apparatus includes a fixed magnet with a second magnetization. An interconnect is further provided which comprises a spin orbit material, wherein the interconnect is adjacent to the stack.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 17, 2023
    Assignee: Intel Corporation
    Inventors: Chia-Ching Lin, Tanay Gosavi, Sasikanth Manipatruni, Dmitri Nikonov, Ian Young
  • Patent number: 11552123
    Abstract: A front-side type image sensor may include a substrate successively including: a P? type doped semiconducting support substrate, an electrically insulating layer and a semiconducting active layer, and a matrix array of photodiodes in the active layer of the substrate. The substrate may include, between the support substrate and the electrically insulating layer, a P+ type doped semiconducting epitaxial layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: January 10, 2023
    Assignee: Soitec
    Inventor: Walter Schwarzenbach
  • Patent number: 11552081
    Abstract: The present application discloses a method for fabricating a semiconductor device with a pad structure. The method includes providing a substrate, forming a capacitor structure above the substrate, forming a plurality of passivation layers above the capacitor structure, forming a pad opening in the plurality of passivation layers, performing a passivation process comprising soaking the pad opening in a precursor, and forming a pad structure in the pad opening. The precursor is dimethylaminotrimethylsilane or tetramethylsilane. Forming the pad structure in the pad opening comprises forming a pad bottom conductive layer comprising nickel in the pad opening and forming a pad top conductive layer on the pad bottom conductive layer. The pad top conductive layer comprises palladium, cobalt, or a combination thereof.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 10, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11549196
    Abstract: There is provided an aluminum nitride laminate member including: a sapphire substrate having a base surface on which bumps are distributed periodically, each bump having a height of smaller than or equal to 500 nm; and an aluminum nitride layer provided on the base surface and having a surface on which protrusions are formed above the apices of the bumps.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: January 10, 2023
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Hajime Fujikura
  • Patent number: 11545477
    Abstract: A chip package includes an interposer comprising a silicon substrate, multiple metal vias passing through the silicon substrate, a first interconnection metal layer over the silicon substrate, a second interconnection metal layer over the silicon substrate, and an insulating dielectric layer over the silicon substrate and between the first and second interconnection metal layers; a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip over the interposer; multiple first metal bumps between the interposer and the FPGA IC chip; a first underfill between the interposer and the FPGA IC chip, wherein the first underfill encloses the first metal bumps; a non-volatile memory (NVM) IC chip over the interposer; multiple second metal bumps between the interposer and the NVM IC chip; and a second underfill between the interposer and the NVM IC chip, wherein the second underfill encloses the second metal bumps.
    Type: Grant
    Filed: February 7, 2021
    Date of Patent: January 3, 2023
    Assignee: iCometrue Company Ltd.
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin
  • Patent number: 11545447
    Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: January 3, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
  • Patent number: 11532571
    Abstract: Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency (RF) ICs.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: December 20, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Plamen Vassilev Kolev, Anil Kumar Vemulapalli, Matthew Deig
  • Patent number: 11532553
    Abstract: A semiconductor structure is disclosed that includes a first conductive line, a first conductive segment, a second conductive segment, and a gate. The first conductive segment is electrically coupled to the first conductive line through a conductive via. The second conductive segment is configured to electrically couple the first conductive segment with a third conductive segment disposed over an active area. The gate is disposed under the second conductive segment and disposed between first conductive segment and the third conductive segment. The first conductive line and the second conductive segment are disposed at two sides of the conductive via respectively. A length of the first conductive segment is greater than a length of the third conductive segment.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hung Shen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin
  • Patent number: 11530353
    Abstract: A quantum dot including a multi-component core including a first semiconductor nanocrystal including indium (In), zinc (Zn), and phosphorus (P) and a second semiconductor nanocrystal disposed on the first semiconductor nanocrystal, the second semiconductor nanocrystal including gallium (Ga) and phosphorus (P) wherein the quantum dot is cadmium-free and emits green light, a mole ratio (P:In) of phosphorus relative to indium is greater than or equal to about 0.6:1 and less than or equal to about 1.0, and a mole ratio (P:(In+Ga)) of phosphorus relative to indium and gallium is greater than or equal to about 0.5:1 and less than or equal to about 0.8:1, a quantum dot-polymer composite pattern including the same, and a display device.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: December 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeyeon Yang, Garam Park, Shin Ae Jun, Tae Gon Kim, Taekhoon Kim
  • Patent number: 11513269
    Abstract: The present invention provides a manufacturing method of a color film substrate and the color film substrate. The manufacturing method includes providing a substrate; forming a first photoresist layer on a first sub-pixel region; forming a quantum dot layer on the substrate, wherein light emission colors of at least two types of quantum dots are respectively different from a light emission color of the first photoresist layer; forming a second photoresist layer and a third photoresist layer on the quantum dot layer in order; and quenching the quantum dot layer to invalidate unshielded quantum dots of the quantum dot layer.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: November 29, 2022
    Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventor: Jie Chen
  • Patent number: 11508421
    Abstract: An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: November 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Mithun Kumar Ramasahayam, Michael J. Gossman
  • Patent number: 11508757
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chih Chiang, Tung-Yang Lin, Ruey-Hsin Liu, Ming-Ta Lei