Abstract: A method of forming a substrate comprises providing a receiver substrate and a donor substrate successively comprising: a carrier substrate, a sacrificial layer, which can be selectively etched in relation to an active layer, and a silicon oxide layer, which is arranged on the active layer. A cavity is formed in the oxide layer to form a first portion that has a first thickness and a second portion that has a second thickness greater than the first thickness. The cavity is filled with a polycrystalline silicon filling layer to form a second free surface that is continuous and substantially planar. The receiver substrate and the donor substrate are assembled at the second free surface, and the carrier substrate is eliminated while preserving the active layer and the sacrificial layer.

Abstract: Embodiments of 3D memory devices and methods for forming and operating the same are disclosed. In an example, a 3D memory device includes a memory stack, a plurality of memory strings, and a plurality of bit line contacts each in contact with a respective one of the plurality of memory strings. The memory stack includes interleaved conductive layers and dielectric layers. Each memory string extends vertically through the memory stack. The conductive layers include a plurality of drain select gate (DSG) lines configured to control drains of the plurality of memory strings. The plurality of memory strings are divided into a plurality of regions that are a minimum repeating unit of the memory stack in a plan view. Each of the plurality of memory strings abuts at least one of the DSG lines.

Abstract: An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer. An electronic device has an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A white space region adjacent the electronic device includes a first P-type region in the semiconductor layer and adjacent the surface. The P-type region has a first sheet resistance and the NWELL region has a second sheet resistance that is greater than the first sheet resistance.

Abstract: A sensor system with a first semiconductor die part and with a second semiconductor die part is proposed, wherein the first semiconductor die part has a microelectromechanical sensor element, wherein the second semiconductor die part covers the microelectromechanical sensor element, wherein the second semiconductor die part has a via for electrically contacting the microelectromechanical sensor element, in particular directly. A method for producing a sensor system is also proposed.

Abstract: A heat pipe is provided as an electrically inactive structure to dissipate heat that is generated by vertically stacked field effect transistors (FETs). The heat pipe is present in an electrically inactive device area which is located adjacent to an electrically active device area that includes the vertically stacked FETs. The heat pipe includes at least one vertical interconnect structure that continuously extends between each tier of the vertically stacked FETs.

Abstract: A light emitting device including a first light source including a plurality of first light emitting structures and a first wavelength converter and configured to emit a first light, a second light source including a second light emitting structure and a second wavelength converter and configured to emit a second light, and a resistor member connected to the first light source and configured to distribute current to the first light emitting structures, in which a color temperature of the first light is configured to be higher than that of the second light, and the first light and second light are configured to have different light intensity.

Abstract: The present invention discloses a semiconductor memory device and a forming method thereof. The semiconductor memory device includes a substrate, a plurality of bit lines, a strip-shaped isolation structure, a conductive residue, a plurality of columnar isolation structures and a plurality of conductive plugs. The bit lines are located on the substrate and extend along the first direction. The strip-shaped isolation structure is located at the ends of the bit lines and extends along the second direction, and the strip-shaped isolation structure includes a seam. In particular, the conductive residue is disposed in the seam. The columnar isolation structures are separated from each other and disposed between the bit lines. The conductive plugs are separated from each other and disposed between the bit lines, in which the conductive plugs and the conductive residue include the same conductive material.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

Abstract: A package comprising a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes a dielectric layer and a plurality of interconnects. The plurality of interconnects includes a first plurality of interconnects configured as a first inductor and a second plurality of interconnects configured as a second inductor. The first integrated device is configured to be coupled to the first inductor. The second integrated device is configured to be coupled to the second inductor. The second integrated device is configured to tune the first inductor through the second inductor.

Abstract: Embodiments of this application relate to a retrosynthesis processing method and apparatus, an electronic device, and a computer-readable storage medium. A retrosynthesis processing method is performed by a computer device. The method includes determining molecular representation information of a target molecule. The method includes inputting the molecular representation information into a target neural network. The method includes performing, via the target neural network, retrosynthesis processing on the target molecule based on the molecular representation information of the target molecule, to obtain a respective retrosynthesis reaction of the target molecule for each step of the retrosynthesis processing.

Abstract: Some embodiments include an integrated assembly. The integrated assembly has a first transistor with a horizontally-extending channel region between a first source/drain region and a second source/drain region; has a second transistor with a vertically-extending channel region between a third source/drain region and a fourth source/drain region; and has a capacitor between the first and second transistors. The capacitor has a first electrode, a second electrode, and an insulative material between the first and second electrodes. The first electrode is electrically connected with the first source/drain region, and the second electrode is electrically connected with the third source/drain region. A digit line is electrically connected with the second source/drain region. A conductive structure is electrically connected with the fourth source/drain region.

Abstract: Moisture hermetic guard ring structures for semiconductor devices, related systems, and methods of fabrication are disclosed. Such devices systems, and methods include a guard ring structure laterally surrounding semiconductor devices of a device layer and metal interconnects of an interconnect layer, the guard ring structure extending through the interconnect layer, the device layer, and a bonding layer adjacent one of the interconnect layer or the device layer the bonding layer, and contacting a support substrate coupled to the bonding layer. Such devices systems, and methods may further include via structures having the same material system as the guard ring structure and also extending through the interconnect, the device, and bonding layers and contacting a support substrate.

Abstract: An example circuit includes a coil structure located on at least a first layer of an integrated circuit (IC); and a circuit component comprising conduction paths. The conduction paths are located on one or more layers separate from the first layer and the first layer and the one or more layers form parallel planes. The conduction paths of the circuit component are oriented to avoid eddy currents in the conduction paths caused by an electric current through the coil structure and form a patterned shield. At least some of the conduction paths define an area, and the coil structure is located within the defined area.

Abstract: A substrate including a support structure. The support structure including a polycrystalline ceramic core and a first adhesion layer coupled to the polycrystalline ceramic core. The support structure further including a conductive layer coupled to the first adhesion layer, a second adhesion layer coupled to the conductive layer, and a barrier layer coupled to the second adhesion layer. The substrate further including a bonding layer coupled to the support structure. The substrate further including a substantially single crystal layer comprising at least one of silicon carbide, sapphire, or gallium nitride coupled to the bonding layer. The substrate further including an epitaxial semiconductor layer coupled to the substantially single crystal layer.

Abstract: Embodiments of the present disclosure provide a quantum dot ligand, a quantum dot material, and a quantum dot light emitting device. In a quantum dot ligand of general formula (I), n is 1, 2, 3, or 4; two of X, Y, and Z are G1 group and G2 group, respectively, and the remaining one is selected from the group consisting of G1 group, G2 group, and hydrogen, wherein the G1 group, for each occurrence, is independently selected from —(CH2)m-L-(CH2)n—R1, wherein R1 is a coordination group, m is 0 to 6, n is 0 to 6, and L is a divalent group or absent; the G2 group, for each occurrence, is independently selected from a C4-20 alkyl having a carbon chain with more than 4 carbon atoms.

Abstract: A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.

Abstract: An integrated circuit includes a first pair of power rails and a second pair of power rails that are disposed in a first layer, conductive lines disposed in a second layer above the first layer, and a first active area disposed in a third layer above the second layer. The first active area is arranged to overlap the first pair of power rails. The first active area is coupled to the first pair of power rails through a first line of the conductive lines and a first group of vias, and the first active area is coupled to the second pair of power rails through at least one second line of the conductive lines and a second group of vias different from the first group of vias.

Abstract: A method of forming a semiconductor device includes performing a first implantation process on a semiconductor substrate to form a deep p-well region, performing a second implantation process on the semiconductor substrate with a diffusion-retarding element to form a co-implantation region, and performing a third implantation process on the semiconductor substrate to form a shallow p-well region over the deep p-well region. The co-implantation region is spaced apart from a top surface of the semiconductor substrate by a portion of the shallow p-well region, and the dee p-well region and the shallow p-well region are joined with each other. An n-type Fin Field-Effect Transistor (FinFET) is formed, with the deep p-well region and the shallow p-well region acting as a well region of the n-type FinFET.

Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.

Abstract: Provided are a method for producing a ceramic sintered body having improved light emission intensity, a ceramic sintered body, and a light emitting device. The method for producing a ceramic sintered body comprises preparing a molded body that contains a nitride fluorescent material having a composition containing: at least one alkaline earth metal element M1 selected from the group consisting of Ba, Sr, Ca, and Mg; at least one metal element M2 selected from the group consisting of Eu, Ce, Tb, and Mn; Si; and N, wherein a total molar ratio of the alkaline earth metal element M1 and the metal element M2 in 1 mol of the composition is 2, a molar ratio of the metal element M2 is a product of 2 and a parameter y and wherein y is in a range of 0.001 or more and less than 0.