Patents Examined by Thinh T Nguyen
  • Patent number: 11127754
    Abstract: A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: September 21, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Go Oike
  • Patent number: 11127935
    Abstract: Disclosed are a display panel, a preparation method thereof and a display device. The display panel includes a display region and a non-display region. The preparation method includes: providing a base substrate; preparing a first metal layer on a side of the base substrate; preparing a first insulation layer on a side of the first metal layer; performing a patterning process on the first insulation layer by using a mask plate to form a plurality of first via holes; preparing a passivation layer on a side of the first insulation layer; performing the patterning process on the passivation layer by using the same mask plate to form a plurality of second via holes, where a vertical projection of each of the first via holes on a plane where the base substrate is located covers a vertical projection of one of the second via holes on the plane.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: September 21, 2021
    Assignee: Shanghai AVIC OPTO Electronics Co., Ltd.
    Inventor: Wenjun Dai
  • Patent number: 11127856
    Abstract: A method for improving breakdown voltage of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) includes biasing a first well of a Field Effect Transistor (FET) to a first voltage. The first well is laterally separated from a second well. An isolation ring is charged to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first well and the second well. A substrate is biased to a third voltage being less than or equal to the first voltage. The substrate laterally extends below the BL and contacts the BL.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 21, 2021
    Assignee: NXP USA, INC.
    Inventors: Xin Lin, Zhihong Zhang, Xu Cheng, Ronghua Zhu
  • Patent number: 11121052
    Abstract: A three dimensional integrated circuit (3D-IC) module socket system includes an integrated Fan-Out (InFO) adapter having one or more integrated passive devices (IPDs) embedded in the InFO adapter. The InFO adapter is also integrated into the 3D-IC module socket system by stacking the InFO adapter between a socket and a SoW package. The InFO adapter with embedded IPDs allows for more planar area of the SoW package to be available for interfacing the socket and provides a short distance between the embedded IPDs and computing dies of the SoW package which enhances a power distribution network (PDN) performance and improves current handling of the 3D-IC module socket system.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Cheng-Chieh Hsieh, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11114466
    Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: September 7, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Sipeng Gu, Jiehui Shu, Haiting Wang
  • Patent number: 11111432
    Abstract: Provided herein are triangular carbon quantum dots with narrow bandwidth emission, methods of making them, and methods of using such triangular carbon quantum dots, such as in multicolored LED displays.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: September 7, 2021
    Assignee: BEIJING NORMAL UNIVERSITY
    Inventors: Louzhen Fan, Fanglong Yuan, Shihe Yang, Zifan Xi
  • Patent number: 11114390
    Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure and a dummy pattern. The substrate includes a first part surrounding a second part at a top view. The first isolation structure is disposed between the first part and the second part, to isolate the first part from the second part. The second isolation structure is disposed at at least one corner of the first part. The dummy pattern is disposed on the second isolation structure. The present invention also provides a method of forming said semiconductor device.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: September 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Hsuan Chang, Ming-Hua Tsai, Chin-Chia Kuo
  • Patent number: 11107980
    Abstract: A top electrode of a magnetoresistive random access memory (MRAM) device over a magnetic tunnel junction (MTJ) is formed using a film of titanium nitride oriented in a (111) crystal structure rather than a top electrode which uses tantalum, tantalum nitride, and/or a multilayer including tantalum and tantalum nitride.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Tang Wu, Wu Meng Yu, Szu-Hua Wu, Chin-Szu Lee, Han-Ting Tsai, Yu-Jen Chien
  • Patent number: 11107909
    Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 31, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Isao Obu, Kaoru Ideno, Shigeki Koya
  • Patent number: 11101378
    Abstract: An Enhancement-Mode HEMT having a gate electrode with a doped, Group III-N material disposed between an electrically conductive gate electrode contact and a gate region of the Enhancement-Mode HEMT, such doped, Group III-N layer increasing resistivity of the Group III-N material to deplete the 2DEG under the gate at zero bias.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 24, 2021
    Assignee: Raytheon Company
    Inventors: Kiuchul Hwang, Brian D. Schultz, John Logan, Christos Thomidis
  • Patent number: 11101212
    Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 24, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dhishan Kande, Qi-Zhong Hong, Abbas Ali, Gregory B. Shinn
  • Patent number: 11094651
    Abstract: Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency (RF) ICs.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: August 17, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Plamen Vassilev Kolev, Anil Kumar Vemulapalli, Matthew Deig
  • Patent number: 11088144
    Abstract: A semiconductor device includes a substrate comprising a plurality of active regions extending in a first direction and a device isolation region electrically isolating the plurality of active regions, a gate trench extending across the plurality of active regions and the device isolation region, a gate structure extending in the gate trench of each of and along opposite sidewalls of the plurality of active regions, a gate dielectric film formed between the gate trench and the gate structure in each of the plurality of active regions, and an insulating barrier film provided in each of the plurality of active regions under the gate trench spaced apart from a lower surface of the gate trench and extending in an extension direction of the gate trench.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyeoung-won Seo
  • Patent number: 11086175
    Abstract: A display device with a narrow frame is provided. A display device with high visibility is provided. A display device with low power consumption is provided. A novel display device is provided. A structure having a stack structure in which a gate driver including a first transistor and a common driver including a second transistor which includes a metal oxide in its channel formation region are stacked has been conceived. Because the gate driver has a larger area than the common driver, part of the gate driver may be formed on the same plane as the common driver.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 10, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kei Takahashi
  • Patent number: 11088073
    Abstract: In some examples, a semiconductor device includes a substrate, an interlayer insulating film, a gate pad provided on the interlayer insulating film, a source electrode that is provided on the interlayer insulating film, source wiring provided on the interlayer insulating film, and gate wiring that is provided on the interlayer insulating film and is electrically connected to the gate pad. The size of the source wiring is not increased, and a high impurity concentration region having a higher impurity concentration than a drift layer is formed on the surface of the substrate at a location directly below the gate pad.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: August 10, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Toshikazu Tanioka, Yasunori Oritsuki, Kenichi Hamano, Naochika Hanano
  • Patent number: 11088141
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a capacitor structure positioned above the substrate, a plurality of passivation layers positioned above the capacitor structure, and a pad structure positioned in the plurality of passivation layers. The pad structure comprises a pad bottom conductive layer comprising nickel and a pad top conductive layer positioned on the pad bottom conductive layer. The pad top conductive layer comprises palladium, cobalt, or a combination thereof.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 10, 2021
    Assignee: Nanya Technology Corporation
    Inventor: Tse-Yao Huang
  • Patent number: 11081504
    Abstract: The present invention provides a display device, including: a display region; a non-display region surrounding the display region; multiple signal lines distributed in the display region; multiple drive chips distributed in the non-display region, each of the drive chips being provided with at least one signal output end; and at least one fan-out line, one end of each fan-out line being connected to the signal output end of one of the drive chips, the other end of each fan-out line being connected to each signal line. The at least one fan-out line is entirely or partially placed over the drive chips. The invention can effectively solve the problems of low reliability of left and right bezels of the display panel and weak antistatic capability, and can make the left and right bezel narrower.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: August 3, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yantao Lu
  • Patent number: 11081537
    Abstract: The present invention provides a substrate and a manufacturing method of the substrate. The substrate includes: a glass base plate; a first base layer on the glass base plate; a light shielding layer on the first base layer; multiple pixel units placed on the first base layer, the pixel units including at least one light transmissive region; and a photomask for exposing the light shielding layer. The photomask is used to expose, develop, and etch away a portion of the light shielding layer on the pixel units which need to communicate with each other, so that multiple grooves are formed in the light shielding layer to make the pixel units communicate with each other.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: August 3, 2021
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yun Yu
  • Patent number: 11081439
    Abstract: According to one embodiment, an integrated circuit includes a chip, a first pin, a second pin, and a third pin. The chip includes an internal circuit and a plurality of pads connected to the internal circuit. The first pin is connected to a first pad among the plurality of pads. The first pin is connected to a power supply provided outside the integrated circuit. The second pin is connected to a second pad among the plurality of pads. The second pin is connected to a ground provided outside the integrated circuit. The third pin is connected to the second pin inside the integrated circuit via a third pad among the plurality of pads. The third pin is insulated from the second pin outside the integrated circuit.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 3, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kentaro Watanabe
  • Patent number: 11075008
    Abstract: Various embodiments predict drug-disease associations. In one embodiment, a plurality of disease similarity matrices and a plurality of disease similarity matrices are accessed. Each of the plurality of drug similarity matrices is associated with a different drug information source. Each of the plurality of disease similarity matrices is associated with a different disease information source. A known drug-disease association matrix is also accessed. The known drug-disease association matrix indicates if a given drug identified is known to treat a given disease. At least one drug-disease association prediction is generated based on the plurality of drug similarity matrices, the plurality of disease similarity matrices, and the known drug-disease association matrix. The at least one drug-disease association prediction identifies a previously unknown association between a given drug and a given disease, and a probability that the given disease is treatable by the given drug.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jianying Hu, Fei Wang, Ping Zhang