Patents Examined by Thinh T Nguyen
  • Patent number: 10784325
    Abstract: A thin film transistor (TFT) to control a light emitting diode (LED) or an organic light emitting diode (OLED) includes a channel region configured as a saddle channel extending between the drain region and the source region of the TFT. The saddle channel is formed by deposition of channel material on a fin structure, and the contour of the saddle channel is defined by the contour of the fin structure. Deposition of the channel material for the saddle channel may be performed by: (i) atomic layer deposition (ALD) of amorphous silicon; (ii) ALD of amorphous silicon followed by annealing to form polycrystalline silicon; or (iii) deposition of indium gallium zinc oxide (IGZO) material by one of ALD, plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), or plasma-enhanced chemical vapor deposition (PECVD).
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: September 22, 2020
    Assignee: INTEL CORPORATION
    Inventors: Khaled Ahmed, Prashant Majhi, Kunjal Parikh
  • Patent number: 10784381
    Abstract: A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p+ region, an n? layer, and an n+ region. The p+ region, the n? layer, and the n+ region follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The n+ region or the p+ region is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the n? layer or of an intermediate layer adjacent to the n? layer and to the p+ region and the first and the second peripheral edges each have a width of at least 10 ?m.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 22, 2020
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Volker Dudek
  • Patent number: 10782575
    Abstract: Array substrate and display panel, and their fabrication methods are provided. The array substrate includes a first base substrate; a pixel electrode over the first base substrate; a first common electrode between the first base substrate and the pixel electrode; and a storage capacitor electrode, between the pixel electrode and the first common electrode and coupled with one of the pixel electrode and the first common electrode. Projections of the first common electrode and the pixel electrode on the first base substrate at least partially overlap with each other.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 22, 2020
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongming Zhan, Xibin Shao, Yu Ma, Chao Tian
  • Patent number: 10784121
    Abstract: Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package generally includes a package substrate; at least one interposer disposed above the package substrate and comprising a plurality of interconnection lines; a programmable IC die disposed above the interposer; a fixed feature die disposed above the interposer; and an interface die disposed above the interposer and configured to couple the programmable IC die to the fixed feature die using a first set of interconnection lines routed through the interposer between the programmable IC die and the interface die and a second set of interconnection lines routed through the interposer between the interface die and the fixed feature die.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: September 22, 2020
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 10777684
    Abstract: A vertical pillar device includes a substrate, one or more pillars, a drain section, and a source section. The one or more pillars include a first end and a second end. The first end is connected to the substrate at a first interface. The substrate and the one or more pillars are made of different materials. The drain section surrounds the one or more pillars near the first end and away from the first interface. The source section connects to the one or more pillars at the second end.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 15, 2020
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Qing Liu
  • Patent number: 10770634
    Abstract: Disclosed are techniques related to reflectors having overall mesa shapes. Such a reflector may be formed over an overall mesa-shaped, layered structure of an apparatus for emitting light. The overall mesa-shaped, layered structure may comprise a mesa complement structure, a first-type doped semiconductor, a light emission layer, and a second-type doped semiconductor arranged in layers. Thus, the reflector may be configured to collimate light that emits from the light emission layer and reaches the reflector through the mesa complement structure.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: September 8, 2020
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventors: Daniel Bryce Thompson, James Small
  • Patent number: 10763389
    Abstract: Described herein are light emitting apparatuses with minimized light emission areas and methods for fabricating such apparatuses. In certain embodiments, the emission area corresponds to an area of an electrical contact and is minimized by minimizing the area of the electrical contact. The electrical contact is configured to receive an electrical signal that causes a light emission layer to generate light. The light emission layer is between a first semiconductor layer and a second semiconductor layer, with the electrical contact being formed on the second semiconductor layer. To protect the second semiconductor layer from damage during an etching process, a conductive body is formed around the electrical contact, where the conductive body is a non-ohmic contact to the second semiconductor layer. The conductive body acts as an etch stop against unintended etching of the second semiconductor layer as a result of an alignment error during the etching process.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 1, 2020
    Assignee: FACEBOOK TECHNOLOGIES, LLC
    Inventor: Daniel Bryce Thompson
  • Patent number: 10763109
    Abstract: A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, encapsulating the polycrystalline ceramic core in a first adhesion shell, encapsulating the first adhesion shell in a conductive shell, encapsulating the conductive shell in a second adhesion shell, and encapsulating the second adhesion shell in a barrier shell. The method also includes joining a bonding layer to the support structure, joining a substantially single crystalline silicon layer to the bonding layer, forming an epitaxial silicon layer by epitaxial growth on the substantially single crystalline silicon layer, and forming one or more epitaxial III-V layers by epitaxial growth on the epitaxial silicon layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 1, 2020
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Cem Basceri, Shari Farrens
  • Patent number: 10763333
    Abstract: A nitride semiconductor device may comprise a p-type layer. The nitride semiconductor device may comprise a first n-type voltage-blocking layer in contact with the p-type layer. The nitride semiconductor device may comprise a second n-type voltage-blocking layer in contact with the first n-type voltage-blocking layer and separated from the p-type layer by the first n-type voltage-blocking layer. A donor concentration in the first n-type voltage-blocking layer may be lower than a donor concentration in the second n-type voltage-blocking layer. A carbon concentration in the first n-type voltage-blocking layer may be lower than a carbon concentration in the second n-type voltage-blocking layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 1, 2020
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Kazuyoshi Tomita, Tetsuo Narita
  • Patent number: 10748853
    Abstract: A flexible display device is disclosed. In one aspect, the display device includes a flexible display panel including a display substrate, wherein the display substrate includes an active area for pixel circuits, an inactive area adjacent to the active area and having a pad area including a plurality of pad terminals, and a thin film encapsulation layer covering the active area. The display device also includes a display driver electrically connected to the pad terminals and a plurality of driving terminals each having a rounding unit. A conductive unit is configured to electrically connect the pad terminals to the respective driving terminals.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 18, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jonghwan Kim, Sangurn Lim
  • Patent number: 10748812
    Abstract: Air-gap containing metal interconnects with selectively-deposited dielectric material are provided. In one aspect, a method of forming an interconnect structure with air-gaps includes: forming interconnect metal lines separated from a first dielectric by a liner and a barrier layer; depositing a capping layer and an inhibitor layer over the interconnect metal lines; patterning the capping layer, inhibitor layer and first dielectric to form the air-gaps between the interconnect metal lines; selectively depositing a second dielectric to form a bridge of the second dielectric over/pinching off the air-gaps, wherein the barrier layer inhibits deposition of the second dielectric along the sidewalls of the interconnect metal lines, and the inhibitor layer inhibits deposition of the second dielectric on top of the interconnect metal lines. An interconnect structure is also provided.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kenneth C. K. Cheng, Koichi Motoyama, Kisik Choi, Chih-Chao Yang
  • Patent number: 10749044
    Abstract: A stacked III-V semiconductor component having a stack with a top, a bottom, a side surface, and a longitudinal axis. The stack has a p+ region, an n? layer, and an n+ region. The p+ region, the n? layer, and the n+ region follow one another in the specified order along the longitudinal axis and are monolithic in design, and include a GaAs compound. The n+ region or the p+ region is a substrate layer. The stack has, in the region of the side surface, a first and a second peripheral, shoulder-like edge. The first edge is composed of the substrate layer; the second edge is composed of the n? layer or of an intermediate layer adjacent to the n? layer and to the p+ region and the first and the second peripheral edges each have a width of at least 10 ?m.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 18, 2020
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Volker Dudek
  • Patent number: 10741439
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hsueh-Chung Chen, Martin J. O'Toole, Terry A. Spooner, Jason E. Stephens
  • Patent number: 10741781
    Abstract: An organic light emitting device can include first and second electrodes formed to face each other on a substrate; a first stack interposed between the first and second electrode and configured with a hole injection layer, a first hole transportation layer, a first light emission layer and a first electron transportation layer which are stacked on the first electrode; a second stack interposed between the first stack and the second electrode and configured with a second hole transportation layer, a second light emission layer, a third light emission layer and a second electron transportation layer which are stacked on the first stack; a third stack interposed between the second stack and the second electrode and configured with a third hole transportation layer, a fourth light emission layer, a third electron transportation layer and an electron injection layer which are stacked on the second stack; and a first charge generation layer interposed between the first and second stacks and a second charge generati
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 11, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Tae Sun Yoo, Hwa Kyung Kim, Hong Seok Choi, Jae Il Song, Mi Young Han, Shin Han Kim, Hye Min Oh
  • Patent number: 10734544
    Abstract: A light emitting diode (LED) apparatus is provided. The LED apparatus includes a light emitting diode, a light conversion layer stacked on the light emitting diode and configured to convert a wavelength of light incident from the light emitting diode, a reflection coating layer stacked on the light conversion layer and configured to pass the light of which the wavelength is converted in light incident from the light conversion layer therethrough and reflecting the other light, and a color filter stacked on the reflection coating layer and configured to correspond to the light conversion layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-hoon Jung, Dae-sik Kim, Sung-yeol Kim, Seung-yong Shin
  • Patent number: 10727433
    Abstract: A display device includes a substrate including a display area and a peripheral area; pixel electrodes in the display area and spaced apart from each other; a pixel-defining layer exposing upper surfaces of the pixel electrodes, covering edges of the pixel electrodes, and including an inorganic insulating material; an auxiliary electrode on the pixel-defining layer; a first intermediate layer on a first pixel electrode among the pixel electrodes; a first opposite electrode on the first intermediate layer; a second intermediate layer on a second pixel electrode from among the pixel electrodes, the second pixel electrode neighboring the first pixel electrode; a second opposite electrode on the second intermediate layer and electrically connected to the first opposite electrode via the auxiliary electrode; a power voltage supply line in the peripheral area; and a connection electrode layer electrically connecting the auxiliary electrode to the power voltage supply line.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: July 28, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Duckjung Lee, Jiyoung Choung, Arong Kim
  • Patent number: 10727139
    Abstract: Techniques facilitating three-dimensional monolithic vertical field effect transistor logic gates are provided. A logic device can comprise a first vertical transport field effect transistor formed over and adjacent a substrate and a first bonding film deposited over the first vertical transport field effect transistor. The logic device can also comprise a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor. The second bonding film can affix the second vertical transport field effect transistor to the first vertical transport field effect transistor. In addition, the logic device can comprise one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: July 28, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Terry Hook, Ardasheir Rahman, Joshua Rubin, Chen Zhang
  • Patent number: 10720526
    Abstract: A method includes etching a first portion and a second portion of a dummy gate stack to form a first opening and a second opening, respectively, and depositing a silicon nitride layer to fill the first opening and the second opening. The deposition of the silicon nitride layer comprises a first process selected from treating the silicon nitride layer using hydrogen radicals, implanting the silicon nitride layer, and combinations thereof. The method further includes etching a third portion of the dummy gate stack to form a trench, etching a semiconductor fin underlying the third portion to extend the trench down into a bulk portion of a semiconductor substrate underlying the dummy gate stack, and depositing a second silicon nitride layer into the trench.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ting Ko, Han-Chi Lin, Chunyao Wang, Ching Yu Huang, Tze-Liang Lee, Yung-Chih Wang
  • Patent number: 10714501
    Abstract: An electronic integrated circuit chip includes a first transistor arranged inside and on top of a solid substrate, a second transistor arranged inside and on top of a layer of semiconductor material on insulator having a first thickness, and a third transistor arranged inside and on top of a layer of semiconductor material on insulator having a second thickness. The second thickness is greater than the first thickness. The solid substrate extends underneath the layers of semiconductor material and is insulated from those layers by the insulator.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 14, 2020
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Jacques Fagot, Philippe Boivin, Franck Arnaud
  • Patent number: 10714431
    Abstract: Semiconductor packages having an electromagnetic interference (EMI) shielding layer and methods for forming the same are disclosed. The method includes providing a base carrier defined with an active region and a non-active region. A fan-out redistribution structure is formed over the base carrier. A die having elongated die contacts are provided. The die contacts corresponding to conductive pillars. The die contacts are in electrical communication with the fan-out redistribution structure. An encapsulant having a first major surface and a second major surface opposite to the first major surface is formed. The encapsulant surrounds the die contacts and sidewalls of the die. An electromagnetic interference (EMI) shielding layer is formed to line the first major surface and sides of the encapsulant. An etch process is performed after forming the EMI shielding layer to completely remove the base carrier and singulate the semiconductor package.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 14, 2020
    Assignee: UTAC Headquarters Pte. Ltd.
    Inventors: Antonio Bambalan Dimaano, Jr., Dzafir Bin Mohd Shariff, Seung Guen Park, Roel Adeva Robles