Abstract: A dynamic random access memory (DRAM) and its manufacturing method are provided. The DRAM includes a buried word line, a bit line, a bit line contact structure, a capacitive contact structure, and an air gap structure. The buried word line is formed in the substrate and extends along a first direction. The bit line is formed on the substrate and extends along a second direction. The bit line contact structure is formed below the bit line. The capacitive contact structure is adjacent to the bit line and surrounded by the air gap structure. The air gap structure includes a first air gap and a second air gap respectively located on a first side and a second side of the capacitive contact structure. The first air gap exposes a shallow trench isolation structure in the substrate. The second air gap exposes a top surface of the substrate.

Abstract: The present disclosure relates to a semiconductor device and a fabricating method thereof, which includes a substrate and a plurality of word lines. The substrate includes a shallow trench isolation and an active structure defined by the shallow trench isolation and the active structure includes a first active area and a second active area. The first active area includes a plurality of active area units being parallel extended along a first direction, and the second active area is disposed outside a periphery of the first active area, to surround all of the active area units. The word lines are disposed in the substrate to intersect the active area units and the shallow trench isolation. The word lines includes first word lines arranged by a first pitch and second word lines arranged by a second pitch, and the second pitch is greater than the first pitch.

Abstract: A method for forming a shallow trench isolation (STI) structure using two individual STI trench etching processes is provided. A first STI etching process forms first trenches with one or more sizes in rows along a first dimension in a silicon substrate. A first dielectric is filled in the first trenches following a first thermal oxidation forming a first liner oxide surrounding the first trenches. A second STI trench etching process forms second trenches with one or more sizes in a second dimension to define active regions separated from each other by the first trenches filled with the first dielectric material and second trenches. A second dielectric is filled in the second trenches following a second thermal oxidation forming a second liner oxide surrounding the second trenches. Active region encroachment caused by the first and second thermal oxidation is reduced by doing the two individual STI trench etching processes.

Abstract: A multi-stack semiconductor device formed to cover a plurality of gate pitches includes: a 1st transistor; a 2nd transistor formed at a right side of the 1st transistor, and isolated from the transistor by a 1st portion of a diffusion break structure; a 3rd transistor formed vertically above or below the 1st transistor; and a 4th transistor formed at a right side of the 3rd transistor, and isolated from the 3rd transistor by a 2nd portion of the diffusion break structure, wherein the 1st portion and the 2nd portion of the diffusion break structure are formed of different material compositions or have different physical dimensions.

Abstract: A semiconductor structure and a method of forming the semiconductor structure are disclosed. Through forming an electrically conductive structure on a trench isolation structure, utilization of a space above the trench isolation structure is achievable, which can reduce the space required in a semiconductor integrated circuit to accommodate the electrically conductive structure, thus facilitating dimensional shrinkage of the semiconductor integrated circuit.

Abstract: The present disclosure provides a structure having a low reflectance surface, wherein the structure comprises: a base plate; and a plurality of inclined rods protruding from a first face of the base plate and inclined relative to a normal line to the first face, wherein the inclined rods are spaced from each other. Travel paths of light beams in the structure may be longer along the inclined rods. As a result, a larger amount of light may be absorbed by the structure having a low reflectance surface. The amount of light-beams as reflected from the structure having a low reflectance surface may be significantly reduced.

Abstract: The present disclosure relates to a method for predicting the permeability of a stratum corneum lipid matrix to a compound. The method includes providing a model of the stratum corneum lipid matrix including ceramides, free fatty acids, cholesterol and water. The model includes 25-45% total ceramides, based on the molar concentration of all components except water, whereof more than 90% are in extended configuration, and wherein 0-30% of the total ceramides are O-acyl ceramides and 100-70% of the total ceramides are non-O-acyl ceramides. The model also includes 25-45% fatty acid and 25-40% of cholesterol, wherein 1-40% of the cholesterol is located by the fatty acid moeity of the ceramides, and 0.2-6 water molecules per ceramide molecule. The method includes providing molecular designators of the compound and calculating, via means of computer simulations, the predicted permeability using the model and the molecular designators.

Abstract: A diode display includes a substrate having a first island and a second island spaced apart from each other, a first pixel disposed on the first island, and a second pixel disposed on the second island. The first pixel includes a first base layer, a first transistor on the first base layer, a first light emitting element electrically connected to the first transistor, and a first encapsulation layer covering the first light emitting element. The second pixel includes a second base layer, a second transistor on the second base layer, a second light emitting element connected to the second transistor, and a second encapsulation layer covering the second light emitting element.

Abstract: According to an aspect of the present inventive concept there is provided a method for forming a first and a second transistor structure, wherein the first and second transistor structures are spaced apart by an insulating wall, and the method comprising: forming on a semiconductor layer of the substrate a first semiconductor layer stack and a second semiconductor layer stack, each layer stack comprising in a bottom-up direction a sacrificial layer and a channel layer, wherein the layer stacks are spaced apart by a trench extending into the semiconductor layer substrate, the trench being filled with an insulating wall material to form the insulating wall; and processing the layer stacks to form the first and second transistor structures in the first and second device regions, respectively, the processing comprising forming source and drain regions and forming gate stacks; the method further comprising, prior to said processing: by etching removing the sacrificial layer of each layer stack to form a respect

Abstract: A method for manufacturing first and second transistors on a semiconductor substrate includes: depositing an interface layer on the semiconductor substrate; depositing a gate insulator layer on the interface layer; depositing a first ferroelectric layer on the gate insulator layer over a first region for the first transistor; depositing a metal gate layer on the gate insulator layer over a second region for the second transistor and on the first ferroelectric layer over the first region for the first transistor; and patterning the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer to form a first gate stack for the first transistor which includes the metal gate layer, first ferroelectric layer, gate insulator layer and interface layer and a second gate stack for the second transistor which includes the metal gate layer, gate insulator layer and interface layer.

Abstract: It is intended to conveniently determine the pharmacokinetics of axitinib and to predict the therapeutic effect of axitinib. The present invention provides a method for determining the pharmacokinetics of axitinib, comprising the step of calculating a predicted pharmacokinetic parameter of axitinib using specific gene polymorphisms and background factors regarding a test subject.

Abstract: According to one embodiment, a semiconductor device comprises a circuit board and a semiconductor package mounted on the circuit board. The semiconductor package comprises a semiconductor chip, a first connector on a bottom surface of the semiconductor package and electrically connected to the semiconductor chip, and a metal bump coupled to the first connector and electrically connected to a second connector on the circuit board. The first connector has a contact surface facing the second connector. The contact surface has a recessed portion into which the metal bump extends.

Abstract: A structure provides a polysilicon resistor under a shallow trench isolation (STI). The structure includes the STI, a resistor in the form of a doped buried polysilicon layer under the STI, and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The structure also includes a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer. A related method is also disclosed.

Abstract: A mechanism is described for facilitating stretchable and self-healing solders in microelectronics manufacturing environments. An apparatus of embodiments, as described herein, includes one or more solders associated with a microelectronics component, where the one or more solders contain a liquid metal and are wrapped in an encapsulation material. The apparatus further includes a substrate coupled to the one or more solders.

Abstract: Catalyst design in asymmetric reaction development has traditionally been driven by empiricism, wherein experimentalists attempt to qualitatively recognize structural patterns to improve selectivity. Machine learning algorithms and chemoinformatics can potentially accelerate this process by recognizing otherwise inscrutable patterns in large datasets. Herein we report a computationally guided workflow for chiral catalyst selection using chemoinformatics at every stage of development. Robust molecular descriptors that are agnostic to the catalyst scaffold allow for selection of a universal training set on the basis of steric and electronic properties. This set can be used to train machine learning methods to make highly accurate predictive models over a broad range of selectivity space. Using support vector machines and deep feed-forward neural networks, we demonstrate accurate predictive modeling in the chiral phosphoric acid-catalyzed thiol addition to N-acylimines.

Abstract: A system can include one or more processors configured to access at least one parameter of a material, generate a plurality of structures of the material using the at least one parameter, determine a state of each structure of the plurality of structures using the at least one parameter, determine a difference between the state of each structure of the plurality of structures and a ground state value, evaluate a convergence condition responsive to determining the difference between the state of each structure of the plurality of structures and the ground state value, and output at least one structure of the plurality of structures responsive to the convergence condition being satisfied.

Abstract: A system, device, and method for predicting a docked position of a target ligand in a binding site of a biomolecule is disclosed. The prediction makes use of a template ligand-biomolecule complex structure in order to predict a target ligand-biomolecule complex structure. The system and device contain modules allowing for the prediction of a target-ligand biomolecule complex structure. A preparation module can receive information identifying a target ligand and a template ligand-biomolecule structure. A pharmacophore matcher module can identify common pharmacophores between the template ligand and the target ligand. A docking module can predict a docked ligand position of the target ligand by overlapping the pharmacophore models of the target ligand and template ligand while the template ligand is in the binding site of the biomolecule. A biomolecule modification module can modify the biomolecule to reduce clashes between the docked target ligand and the biomolecule.

Abstract: A method of manufacturing a semiconductor package includes forming an encapsulant covering at least a portion of each of an inactive surface and side surface of a semiconductor chip, the semiconductor chip having an active surface on which a connection pad is disposed and the inactive surface opposing the active surface; forming a connection structure having a first region and a second region sequentially disposed on the active surface of the semiconductor chip, and the connection structure including a plurality of redistribution layers electrically connected to the connection pad of the semiconductor chip and further including a ground pattern layer; and forming a metal layer disposed on an upper surface of the encapsulant, and extending from the upper surface of the encapsulant to a side surface of the first region of the connection structure.

Abstract: A method for manufacturing a display device includes a pixel circuit formed on a substrate, wherein a manufacturing process of the pixel circuit includes a patterning step of a metal film performed in the following procedures (a) to (e): (a) forming the metal film on the substrate; (b) forming a first resist pattern on the metal film by a photolithographic method; (c) etching the metal film with the first resist pattern to form a first metal pattern; (d) forming by the photolithographic method on the metal film formed in the first metal pattern, a second resist pattern including a pattern shape smaller than a pattern shape of the first resist pattern; and (e) etching the metal film with the second resist pattern to form a second metal pattern.

Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.