Abstract: Several embodiments of electrical circuit devices and systems with clock distortion calibration circuitry are disclosed herein. In one embodiment, an electrical circuit device includes clock distortion calibration circuitry to calibrate a clock signal. The clock distortion calibration circuitry is configured to determine when one or more duty cycle calibration (DCC) conditions are met. When the DCC condition(s) are met, the clock distortion calibration circuitry is configured adjust a trim value associated with at least one of first and second duty cycles of first and second voltage signals, respectively. In some embodiments, the clock distortion calibration circuitry is configured to calibrate at least one of the first and the second duty cycles of the first and the second voltage signals using the adjusted trim value to account for duty cycle distortion encountered across various voltages and/or temperatures while the electrical circuit devices and/or systems remain in a powered on state.

Abstract: Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I/O pin (connected to an I/O line) or a CAP pin (connected to a storage capacitor). Embodiments may utilize a hybrid buffer circuit that utilizes an effectively bi-directional PFET pull-up device coupled between the swappable pins A and B. Two open-drain NFETs pull-down devices are used, one on either side of the PFET and coupled to a respective pin (A or B), but with only one NFET being selected to be operable based on pin-determination flag signals from the pin detection circuitry. Such a hybrid buffer circuit would consume significantly less IC area than two complete conventional buffers, resulting in less leakage and less yield loss.

Abstract: When a bias voltage of a substrate is generated, an output voltage of a charge pump is controlled at an appropriate level, resultingly reducing a consumption current. The charge pump generates a predetermined output voltage from a predetermined DC power supply. A clock generator outputs a clock for operating the charge pump. A voltage monitoring unit monitors the output voltage of the charge pump and controls the clock output from the clock generator such that the output voltage is maintained within a predetermined range. A voltage regulator generates the bias voltage from the output voltage of the charge pump.

Abstract: An electronic device and a method of controlling an electronic device are provided. The electronic device includes a first transistor having a first resistor, second resistor, first transistor, and second transistor. The second resistor is connected to the first resistor. The first transistor is connected to the first resistor in parallel and has a first bulk. The second transistor is connected to the second resistor in parallel and has a second bulk. The first bulk of the first transistor receives a first voltage and the first bulk of the second transistor receives a second voltage. The first voltage and the second voltage are different.

Abstract: The present disclosure relates to the field of analog integrated circuit technology. A digital and analog mixed signal control circuit for eliminating a degenerate metastable state of a self-biased bandgap reference circuit utilizes a digital-to-analog converter module with low-power consumption and flexibly customized accuracy as needed, a delay switch, and a non-volatile memory cell to directly control and clamp a circuit node at the degenerate metastable state in the bandgap reference circuit module, and to release the clamping after a certain delay. Such control mechanism effectively prevents the self-biased bandgap reference circuit with an operational amplifier from entering the degenerate metastable state, and enhance robustness of the circuit, such that the reference circuit is capable of starting normally under various conditions, which improves the performance and yield of the products.

Abstract: A clock signal conversion circuit includes an amplification circuit configured to amplify a differential clock signal having sub rail-to-rail voltage swings relative to a supply voltage, such that an amplified differential clock signal output by the amplification circuit has complementary positive and negative signal components with full rail-to-rail voltage swings relative to the supply voltage.

Abstract: A pulse power supply device includes pulse power supplies each of which outputs a monopolar pulse voltage, and transformers. The transformers include primary windings, secondary windings, and tertiary windings, and one pulse power supply is connected to one primary winding on a one-to-one basis. The secondary windings are sequentially connected in series, and a load is connected to both ends of the secondary windings. The tertiary windings are sequentially connected in series, and a magnetic reset circuit is connected to both ends of the tertiary windings. The magnetic reset circuit includes a magnetic reset power supply and an impedance changing circuit that is for limiting an induced current that can be caused to flow by a voltage induced in the tertiary windings. An impedance changing circuit is configured to be able to change an impedance.

Abstract: Operating a bi-directional double-base bipolar junction transistor (B-TRAN). One example is a method comprising: conducting a first load current from an upper terminal of the power module to an upper-main lead of the transistor, through the transistor, and from a lower-main lead of the transistor to a lower terminal of the power module; and then responsive assertion of a first interrupt signal, interrupting the first load current from the lower-main lead to the lower terminal by opening a lower-main FET and commutating a first shutoff current through a lower-control lead the transistor to the lower terminal; and blocking current from the upper terminal to the lower terminal by the transistor.

Abstract: A circuit includes: a first load circuit and a second load circuit coupled in parallel between a first node and a reference voltage node, where the first load circuit and the second load circuit are configured to receive a first input signal and a second input signal, respectively; a first pass device and a first switch coupled in series between a voltage supply node and the first node; a second pass device and a second switch coupled in series between the voltage supply node and the first node; and an amplifier, where a first input terminal and a second input terminal of the amplifier are configured to be coupled to a reference input voltage and the first node, respectively, where an output terminal of the amplifier is coupled to a first control terminal of the first pass device and a second control terminal of the second pass device.

Abstract: A pulse generator comprising: a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; and a controller arranged to activate the plurality of switching elements in a predetermined sequence so as to generate a predetermined pulse waveform at a pulse generator output. The switching elements of the signal generating arm and the inductor together form a pulse synthesizer that takes the signal from the controller and uses it to synthesize an output pulse. Compared with conventional transmitter architectures, the functions of the upconversion mixer, the DAC, and the power amplifier are all performed by a single simplified circuit. This is both area efficient and power efficient.

Abstract: A semiconductor integrated circuit device includes a current leakage detector, a leakage compensation pulse generator, and a leakage compensation voltage generator. The current leakage detector is configured to compare an internal voltage signal with a plurality of reference voltage signals with different levels to generate a current leakage state signal. The leakage compensation pulse generator is configured to generate a bias level compensation signal based on the current leakage state signal and a temperature state signal. The leakage compensation voltage generator is configured to generate the internal voltage signal based on the bias level compensation signal.

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

Abstract: One example discloses a level-shifter circuit, comprising: a pre-driver stage configured to receive differential inputs and generate differential pre-driver outputs; a first output stage coupled to receive the differential pre-driver outputs and generate a single-ended first stage output; a second output stage coupled to receive the differential pre-driver outputs and generate a single-ended second stage output; and wherein the first and second stage outputs together form a differential output.

Abstract: Provided is a zero crossing point signal output method, including: continuously receiving zero crossing point square wave signals, and periodically sampling zero crossing point square wave signals at a predetermined sampling frequency; acquiring sampling numbers of 1st to Mth zero crossing point square wave signals to obtain an average sampling number S, and calculating a first zero crossing point interval T1; setting a zero crossing point signal output interval as the first zero crossing point interval T1; continuously outputting zero crossing point signals with an interval being the zero crossing point signal output interval; obtaining sampling numbers of M+1th to M+Nth zero crossing point square wave signals, calculating a difference value between each of the sampling numbers and S, and obtaining an accumulated difference value ?s through calculation; when ?s is not within a predetermined change range, obtaining a second zero crossing point interval T2 and setting the zero crossing point signal output inte

Abstract: According to one embodiment, electronic circuitry includes a semiconductor switching element; and a driving circuit configured to supply a current to a control terminal of the semiconductor switching element and to adjust a magnitude of the current supplied to the control terminal based on a voltage at the control terminal.

Abstract: This disclosure describes circuits and techniques for identifying potential problems with control signals for power switches. More specifically, this disclosure describes the use of registers, e.g., volatile or non-volatile storage elements, configured to count the rising and/or falling edges of pulse modulation (PM) signals within driver circuits or other control circuits. By counting the edges of PM signals within driver circuits, signaling problems can be identified based on mismatch between different counters. The techniques may be used by a driver circuit to detect circuit problems, or readout of the registers can be done after device failure, in order to help identify whether signaling problems may have caused the device failure.

Abstract: A semiconductor device includes a regulator circuit, a wire, n load circuits, and an analog circuit. The wire is connected to the regulator circuit and including n connection nodes (n is an integer of 2 or more). The n load circuits are connected to the n connection nodes, respectively. The analog circuit is connected between the n connection nodes and the regulator circuit. The analog circuit is configured to generate an average voltage of n voltages at the n connection nodes. The regulator circuit is configured to generate an output voltage supplied to the wire based on the average voltage generated by the analog circuit.

Abstract: In an example driver circuit, one of two current sources coupled between a supply voltage and one output node is disabled during a driver disable time period (tpz) while the other continues to operate during a pre-charge monopulse time period (td) within tpz. A third current source on the other side of the driver circuit and coupled to ground is also disabled during tpz. During td, the following components are enabled: a charge current source coupled between the supply voltage and a second output node; a pair of current switches respectively coupled to the output nodes; and a pair of pull-down switches respectively coupled to control terminals of the current switches. After tpz, during a compensation time period (tcomp), the current sources enabled during td are disabled and a compensation current source is enabled. After tcomp, the compensation current source is disabled.

Abstract: Implementing a series gate resistor in a switching circuit results in several performance improvements. Few examples are better insertion loss, lower breakdown voltage requirements and a lower frequency corner. These benefits come at the expense of a slower switching time. Methods and devices offering solutions to this problem are described. Using a concept of bypassing the series gate resistor during transition time, a fast switching time can be achieved while the above-mentioned performance improvements are maintained.

Abstract: An arrangement of conduction-cooled travelling wave tubes includes multiple travelling wave tubes mounted on a common base, wherein the travelling wave tubes are thermally connected to the base so that during operation of the travelling wave tubes the base forms a heat sink for the travelling wave tubes, and the base is designed to accommodate multiple travelling wave tubes in terms of their dimensions along their beam axes so as to increase the number of travelling wave tubes per surface area unit of the base.