Abstract: Aspects of the present disclosure include a hybrid circuit, including a first current sink configured to sink a zero temperature coefficient (ZTC) current, a second current sink configured to sink a positive temperature coefficient (PTC) current, a first transistor configured to provide a first current, a second transistor configured to provide a second current, a third transistor configured to provide a third current mirroring the ZTC current, a fourth transistor configured to provide a sum current of the first current and the third current, and a current mirror configured provide a hybrid current mirroring the sum current.

Abstract: A power managing system and method are provided. When an under voltage lockout circuit determines that a common voltage of the power managing system is lower than a first lockout voltage, the under voltage lockout circuit outputs a first under voltage lockout signal for controlling one of a plurality of power converters that supplies a highest output voltage to rapidly reduce its output voltage to a zero value. Then, the under voltage lockout circuit outputs a second under voltage lockout signal for controlling another one of the power converters that supplies a lowest output voltage to gradually reduce its output voltage to the zero value.

Abstract: The present disclosure provides an abnormal voltage monitoring device, a storage device, and a vehicle. The abnormal voltage monitoring device comprises a voltage divider configure to receive an input voltage from a voltage generator and output a first distribution voltage based on the input voltage, a second bandgap reference generation circuit configured to output a reference voltage, and a monitoring circuit configured to receive the first distribution voltage from the voltage divider and the reference voltage from the second bandgap reference generation circuit, and output an alarm signal responsive to comparing a voltage level of the first distribution voltage with that of the reference voltage. The voltage generator comprises a first bandgap reference generation circuit, and the second bandgap reference generation circuit is configured to generate the reference voltage differently than the first bandgap reference generation circuit.

Abstract: A reference signal generator having high order temperature compensation includes: first and second transistors generating a proportional to absolute temperature (PTAT) signal and at least one complementary to absolute temperature (CTAT) signal according to at least one bandgap related to the first and second transistors; a feedback network coupled to the first and second transistors; an amplifier circuit configured to linearly superimpose the PTAT signal and the CTAT signals via the feedback network, to generate a reference signal; a second order adjustment circuit including a third transistor controlled by a bias voltage, to generate an adjustment current for adjusting the reference signal; and a third order adjustment circuit configured to adjust the bias voltage according to a temperature under test, for adjusting the adjustment current, to adjust the reference signal, such that a variation of the reference signal is smaller than a predetermined variation range within a temperature range.

Abstract: In an example, an apparatus includes an error amplifier, a buffer, a transistor, and a current-mode feedforward ripple canceller (CFFRC). The error amplifier has an amplifier output, a first input, and a second input, the error amplifier second input configured to receive a reference voltage. The buffer has a buffer input and a buffer output, the buffer input coupled to the error amplifier output. The transistor has a gate, a source, and a drain, the gate coupled to the buffer output, the drain coupled to the first input. The transistor is configured to receive an input voltage (VIN) at the source and provide an output voltage at the drain. The CFFRC has a CFFRC input and a CFFRC output, the CFFRC output coupled to the gate, and the CFFRC input configured to receive VIN.

Abstract: A switch activation system including a charge pump, a load monitor, and a switch driver. The charge pump drives a negative voltage node to a predetermined negative voltage level. The load monitor monitors the charge pump and to assert a break done signal after the charge pump begins driving the negative voltage back to the predetermined negative voltage level after being increased. The switch driver turns on a first electronic switch in response to assertion of a corresponding activation signal and assertion of the break done signal. The break done signal is asserted only after electronic switches being turned off are fully turned off to avoid conflict. The charge pump operates at a frequency based on a difference between a voltage level of the negative voltage node and the predetermined negative voltage level to drive the negative voltage node back to its predetermined level within a predetermined period of time.

Abstract: A power supply management device includes an internal power supply circuit, switches, a comparator circuit, and a control circuit. The internal power supply circuit is configured to output a first supply voltage to a node. The switches are coupled between the node and a plurality of first circuits. The comparator circuit is configured to compare a voltage on the node with a reference voltage when the node does not receive the first supply voltage to generate a flag signal. The control circuit is configured to determine whether the node receives a second supply voltage from an external power supply circuit according to the flag signal. If the node receives the second supply voltage, the control circuit is further configured to turn off the internal power supply circuit and gradually turn on the switches, in order to provide the second supply voltage to the first circuits via the switches.

Abstract: A bandgap reference circuit includes a plurality of current sources including different temperature coefficients, a first trimmer, and a mixer. The first trimmer adjusts current amounts for a plurality of currents, which are individually output from each of the plurality of current sources, to be equal to each other. The mixer adjusts an aggregate ratio and combines the plurality of currents based on the aggregate ratio.

Abstract: A signal generating device including a first circuit coupled between a first reference voltage and a second reference voltage and arranged to generate a first current to a first BJT; a first control circuit connected to the first BJT and arranged to adjust the first current. The first circuit outputs a part of a temperature-dependent signal on an output terminal, and includes: a first active device having a first and a second connecting terminal coupled to the first BJT; a second active device having a first connecting terminal coupled to the first BJT, and a second connecting terminal coupled to a second reference voltage; a first amplifier having an input terminal coupled to the first BJT, and an output terminal coupled to the control terminal of the first active device; and a second control circuit coupled to the first circuit for controlling the temperature-dependent signal according to the first current.

Abstract: A duty cycle correction circuit, and method of operating the same, to correct the duty cycle of an input clock signal having a frequency divided-down from a reference clock by an odd-valued integer. A delay stage outputs the input clock signal delayed by one half-cycle of the reference clock, and a logic circuit outputs an extended clock signal by a logical OR of the input and delayed clock signals. A latch latches the extended clock signal when enabled by the reference clock, and a flip-flop latches the extended clock signal responsive to the reference clock. A gate selects the latch output or the flip-flop output based on the state of the delayed clock signal as an intermediate signal. A multiplexer generates the output clock by selecting between the intermediate signal and the input clock signal in alternating reference clock phases.

Abstract: A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.

Abstract: A signal processing apparatus includes a signal processing circuit configured to process a signal obtained from a voltage bus, a high voltage circuit configured to withstand a voltage stress when a high voltage is applied to the voltage bus, and a bypass circuit configured to bypass the high voltage circuit when a low voltage is applied to the voltage bus.

Abstract: Methods and systems for selecting voltage for a substrate connection of a bypass switch include a bulk voltage generation circuit coupled externally to the regulator. The bulk voltage generation circuit is configured to control selection of a voltage from among an Input/Output (I/O) supply voltage and a core supply voltage for a substrate connection of a bypass switch of the regulator. The bulk voltage generation circuit is configured to select the voltage for the substrate connection of the bypass switch based on a mode of operation of the regulator and at least one of a presence or an arrival sequence of the I/O supply voltage and the core supply voltage.

Abstract: A system for regulating voltage includes an electronic fuse including a switching component and an active control circuit connected to the switching component, the control circuit configured to open the switching component based on at least an overcurrent condition. The system also includes a voltage regulation component connected to the switching component, the voltage regulation component configured to regulate a voltage across the switching component by applying a voltage to the switching component based on a measured voltage drop across the switching component, and a desired load voltage.

Abstract: A radio frequency (RF) power detector is disclosed. The RF power detector includes an envelope detector having an RF signal terminal and a current mode terminal, wherein the envelope detector is configured to detect peak voltages of an RF signal at the RF signal terminal. Further included is a detector current mirror having a first mirror branch coupled to the current mode terminal and a second mirror branch configured to create a detector current that is proportional to a branch current through the first mirror branch in response to peak voltages detected by the envelope detector.

Abstract: Sub-threshold current reduction circuit (SCRC) switches and related apparatuses and methods are disclosed. An apparatus includes an electronic circuit, a first set of SCRC switches, and a second set of SCRC switches. The electronic circuit includes first circuitry and second circuitry. The first set of SCRC switches are at one or more SCRC regions of an integrated circuit device including the electronic circuit. The first set of SCRC switches are configured to provide power to the first circuitry. At least one second SCRC switch of the second set of SCRC switches is positioned between one of the first set of SCRC switches and another of the first set of SCRC switches. The second set of SCRC switches is configured to provide power to the second circuitry.

Abstract: An internal voltage generation circuit includes a shifting source voltage generation circuit configured to generate a shifting source voltage having a voltage level that falls as a voltage level of a power supply voltage rises during a period when the power supply voltage is lower than a preset voltage level. The internal voltage generation circuit also includes an internal voltage regulator configured to generate a driving signal through a level shifting operation that is performed according to the shifting source voltage received when driving an internal voltage and configured to drive the internal voltage based on the driving signal.

Abstract: Aspects of the present disclosure are directed to voltage drop compensation for power supplies. One method includes sensing each voltage, via a voltage sensor, of a plurality of voltages from different areas of circuit components prior to the voltage reaching a voltage regulator, receiving, at a voltage manager, a sensed voltage magnitude from the voltage sensor for at least one of the plurality of voltages, receiving, at a voltage manager, data for a number of characteristics of the circuitry components, and selecting a correction voltage to be provided to the voltage regulator based on the sensed voltage magnitude from the voltage sensor for the at least one of the plurality of voltages and data for at least one of the characteristics of the circuitry components.

Abstract: Aspects of the present disclosure are directed to multi-referenced power supplies. One method includes sensing each voltage, via a voltage sensor, of plurality of voltages from different areas of circuit components prior to the voltage reaching a voltage regulator, receiving, at a voltage manager, a sensed voltage magnitude from the voltage sensor, and selecting a feedback voltage to be provided to the voltage regulator based on the sensed voltage magnitude from the voltage sensor for the at least one of the plurality of voltages.

Abstract: A mirror clamp circuit includes a comparator having a first input terminal connectable to a first control terminal of a transistor having the first control terminal connected to the other terminal of a resistor of which one terminal is fed with an output voltage and a first terminal fed with a reference potential and a second input terminal fed with a reference voltage, a transistor switch having a second control terminal fed with a control terminal voltage based on a comparison signal output from the comparator and inserted between the first control terminal and the reference potential, an OR circuit fed with a signal based on the control terminal voltage and the output voltage, and a current feeder configured to change the amount of current fed to the comparator based on the output of the OR circuit.