Abstract: An analog-to-digital converter includes a charge coupled device comparator receiving an analog signal which is to be converted to an eight bit binary word. An eight bit charge coupled device shift register addresses an eight bit digital-to-analog converter through eight separate resettable latches to generate a reference signal which is compared in successive approximations to the analog signal by the charge coupled device comparator to generate each binary bit of the eight bit word. Sensitivity of the charge coupled device comparator is enhanced by the use of charge coupled regenerative feedback to generate each binary bit of the eight bit binary word, which is read serially into an output register. The charge coupled device comparator decides whether each bit of the eight bit binary word is to be a logic one or a logic zero by comparing the analog input signal with reference signals selected in successive approximations by a shift register addressing the digital-to-analog converter.
Abstract: A circuit for detecting leading or lagging phase relationship between first and second two-level input signals at each level transition of both of said input signals and comprising first and second voltage comparators each having first and second input terminals and a single output terminal and each responsive to signals of equal and non-equal logic levels supplied to the first and second input terminals thereof to produce an output signal having high and low logic levels, respectively. First and second input signals are supplied to the first input terminals of the first and second voltage comparators, respectively. A pulse generator responds to each level transition of said first input signal to produce a clock pulse.
Abstract: A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.
June 11, 1979
Date of Patent:
April 20, 1982
International Business Machines Corporation
Richard B. Merrill, Lewis M. Terman, Yen S. Yee
Abstract: In a folding circuit of an analog-to-digital converter a chain of emitters of transistors which are interconnected by threshold elements and fed by direct current sources are used to reduce the distortion. The circuit is controlled by a current source which produces the input signal.
Abstract: This invention relates to a digital-analog interface for insertion between the control circuit of a moving element and a transmitter of digital control signals.This interface comprises an inductive detector of the actual position of the moving element. The inductive detector has a single primary winding directly connected to an a.c. source and two secondary windings. The detector secondary windings are connected in parallel to one input of a summing circuit, through a first resistance of fixed value and through a second resistance of adjustable value, respectively. Means responsive to the transmitter digital control signals are provided to adjust the value of the second resistance. The output of the summing circuit is connected to the control circuit of the moving element.
December 5, 1978
Date of Patent:
April 6, 1982
Societe Nationale Industrielle Aerospatiale
Michel Durandeau, Norbert Voisin, Jean P. Verdier
Abstract: The idle channel for a speech encoder is detected by the detection, at the encoder comparator output, of zero-level traversals caused by noise transient signals appearing at the analog input of the encoder. In response to the detection of an idle channel, the encoder is caused to output a PCM code sample corresponding to a zero amplitude analog signal. In order that a speech signal passing through zero amplitude during the sampling period not be confused with an idle channel condition, the detection circuit responds only to a plurality of zero-level traversals.
Abstract: A digital-to-analog converter which is effective for an interpolative decoder for decoding a linear PCM signal is disclosed. An output signal of a binary rate multiplier which develops signals of several less-significant bits of the linear PCM signal onto a time axis is directly applied to a driver circuit, by which is driven the segment of a ladder resistance network corresponding to the least significant bit, the ladder resistance network having segments corresponding to signals of several more-significant bits of the linear PCM signal. Thus, an adder for the digital addition between the output signal of the binary rate multiplier and the signals of the several more-significant bits is dispensed with.
Abstract: The disclosed high resolution analog to digital converter circuit has an integrator circuit responsive to the unknown analog input. The integrator circuit is operated for a fixed period of time during which, on a periodic basis, a predetermined charge is dumped from the integrator circuit capacitor. A counter is incremented each time a dump occurs and the counter value at the end of the fixed period is related to the high order digits of the digital value for the unknown analog signal. A digital number corresponding to the output level of the integrator is determined by a successive approximation circuit both before and just after the fixed period. The difference between the two values determined by the successive approximation circuit is related to the low order digits of the digital value for the unknown analog signal.
Abstract: Circuitry for producing the signals necessary for driving and controlling a synchro-resolver is disclosed. The circuitry includes a reference generator (84) which is driven by an AC reference signal and thus, the resulting output DC reference voltage on line (82) is locked to the AC reference signal. The DC reference voltage is then combined with a computer generated digital command signal by a MDAC (Multiplying Digital to Analog Converter) (74) to provide a control signal which varies around a selected reference level. A pulse-width modulator (112) provides a high frequency square wave output which square wave is pulse-width-modulated by the AC reference voltage. The pulse-width-modulated high frequency square wave is then provided to an amplitude modulator circuit (106) where the high frequency square wave is itself amplitude modulated by the control signal.
Abstract: A signal converter includes a generator for generating first and second clock signals having recurrence periods equal to each other and phases different from each other, an input for receiving as a signal to be converted a signal which has signal levels not lower than a predetermined level during an arbitrary period of time, a counter for counting the first clock signals from the generator in a period of time corresponding to the signal period of time, and an output arrangement. The output arrangement provides for delivering either of two signals in dependence on which of time intervals determined by the first and second clock signals an end of said signal period of time lies in, whereby signals of the counter and the output arrangement are used as a converted signal.
Abstract: A data processing system is disclosed in which analog input information or data is fed to a plurality of analog memories each of which receives different input information and has different data processing characteristics and in which discrete analog signal values from the analog memories are converted into digital information.
Abstract: Signal information is converted between analog and digital form in a two-step process employing conversion apparatus having stable, but not necessarily highly accurate components. The component tolerances on such conversion apparatus are much greater than those on such conversion apparatus are much greater than those normally allowed on conventional conversion apparatus of equal accuracy. In an A/D conversion, an analog signal is first converted into an (n+m)-bit digital word in a special purpose digital code unique to the specific A/D conversion apparatus. The (n+m)-bit word is then translated into an n-bit word in binary digital code in accordance with a predetermined relationship therebetween. In a D/A conversion, an n-bit digital word in a binary digital code is first translated into a corresponding (n+m)-bit digital word in the special purpose digital code.
Abstract: An electronic digital tape measure includes a flexible tape, a detector, and a digital display. A keyboard unit and a control circuit may be further included for acting as an electronic calculator. The flexible tape is constructed by allocating a number of magnetic balls a predetermined space from each other and by locating a number of non-magnetic balls to provide the space therebetween. The chain of the balls is covered by flexible synthetic resin or the like. While the flexible tape has no special structure, a holding member is provided within the detector for grasping the flexible tape to be driven in unison with the movement of the flexible tape.
Abstract: A recirculating remainder analog-to-digital conversion method and apparatus are disclosed for converting an analog signal into a digitally encoded signal representing the analog signal as two or more digits in a selected number base. Conversion is based on employing two gain factors, one dependent on the digital code used for encoding digits, such as a binary code, and the other dependent on the selected number base for the digits, such as decimal, and by selectively amplifying by the gain factors in a predetermined sequence for producing the signals that are recirculated during conversion of the analog signal into the digitally encoded signal. A method and apparatus are also disclosed for nulling errors in recirculating remainder converters introduced by operation of the converter circuitry by transferring signals through the circuitry once at one polarity and again at the opposite polarity during conversion of the analog signal into the digitally encoded signal.
Abstract: An A-D converter in which an input analog signal is converted by a first A-D converting circuit into a digital signal to obtain a high-order digit output, the high-order digit output is re-converted by a D-A converting circuit into an analog signal and the difference between the re-converted analog signal and the input analog signal is amplified and then converted by a second A-D converting circuit into a digital signal. An ideal voltage which would be produced when the input to the D-A converting circuit is separately applied for each bit of the D-A converting circuit is provided from a reference voltage source. The difference between the output derived from the D-A converting circuit in response to the application of the input thereto for each bit and the voltage of the reference voltage source corresponding to the D-A converting circuit output is converted by the second A-D converting circuit into a digital signal, so that an error signal is obtained.
Abstract: Apparatus is disclosed for detecting the relative position or displacement between two movable bodies, wherein a reader or sensor mounted on one of the two bodies reads a code pattern on the other body. A code pattern is provided that represents a binary-coded base-n number, each digit of a base-n number being represented by each of first, second, third, . . . , and m-th unit-distance codes (where m being the least submultiple except 1 of the base-n number system), these codes in turn being converted into a common binary code so that the relative position or displacement between the two bodies may be represented by the binary-coded base-n number.
Abstract: An analog-to-digital converter is disclosed which utilizes a successive approximation register. The operation of the successive approximation register is so controlled that any analog signal within a dynamic range requiring more bits than the successive approximation register can hold can nonetheless be accurately converted within a predetermined tolerance.
Abstract: A companded stacked DAC is provided which can be used in an A-law or .mu.-law conversion merely by selection. The companded DAC is inherently monotonic and can be integrated with field effect transistors. The current sources of the DAC are switched to only one of two buses. The stacked DAC includes a chord DAC and a step DAC. The two buses which the chord DAC is connected to are maintained at approximately equal voltages by the use of a reference amplifier. The companded DAC uses successive approximation when converting.
Abstract: To convert a sample of an amplitude-modulated voltage wave into binary pulses, the sample is simultaneously compared in two coders with two sets of threshold voltages of positive and negative polarity, respectively. Either one of the two coders yields in unbroken succession of pulses, having the same polarity as the sample, whereas the other coder produces a combination of both positive and negative pulses. Following inversion of the pulses issuing from one coder, and upon suppression of the pulses of one polarity (e.g. negative), the two pulse trains are combined into a series of bit groups each representing the absolute amplitude value of a respective sample. The final step in the processing of any sample is the generation of a sign bit in accordance with the polarity of the unipolar pulse train emitted by one of the coders; this sign bit is then transposed to the beginning of the corresponding group of amplitude bits.
September 11, 1979
Date of Patent:
January 12, 1982
CSELT - Centro Studi e Laboratori Telecomunicazioni S.p.A.
Giancarlo Babini, Bruno Fabbri, Paolo Lucchini
Abstract: An integrating analog-to-digital converter for producing a digital output signal representing the value of an analog input signal which may have either a positive or negative polarity. The converter uses a switching circuit to reverse an integrator capacitor between charge and discharge periods so that the same input-signal-controlled current source can be used to both charge and discharge the capacitor. This results in inherent zero calibration because any offset errors during the charge cycle are cancelled out by equal and opposite offsets during the discharge cycle.