Abstract: An integrated-circuit 12-bit digital-to-analog converter comprising binarily-scaled constant-current sources with associated switch cells employing bipolar transistors to direct the bit currents either to a summing bus or to ground. The switch cells include a first differential transistor pair to translate a single-ended binary logic signal to double-ended (balanced) format, and a second, fully-balanced differential pair operated by the balanced logic signal to direct the bit current correspondingly. A bias-generating circuit maintains a constant collector-base voltage at the constant-current source. The threshold voltage for the logic signals can be set for TTL logic or, by pin-programming, for CMOS logic of either low-voltage or high-voltage type.

Abstract: An analog-to-digital conversion system uses a fast analog-to-digital converter having a resolution less than the system resolution to convert the difference between a previously predicted value and the current analog value. The converted difference is summed with the predicted value to compute the actual value of the analog input signal to a resolution greater than that of the fast analog-to-digital converter. The high resolution digital value thus obtained becomes the predicted value for the next conversion. This predicted value is converted by a digital-to-analog converter having the same accuracy but not the same resolution as the system output to an analog signal which is compared with the input analog signal to obtain a difference signal. This difference signal is sampled and held to provide the input to the fast analog-to-digital converter.

Abstract: A method is described for electrically converting an analog signal into a digital representation in a manner that maximizes noise rejection. The digital representation is formed from a preselected number of discrete points corresponding to sampled approximations of the analog signal. In establishing the magnitudes of the respective points, digital samples of the analog signal are taken at a predetermined number of discrete coordinates along the analog signal on either side of the respective discrete points. The predetermined number of coordinates are averaged and employed as corresponding approximations for the respective discrete points in the digital representative reproduction of the analog signal. The effects of harmonics of power line frequencies associated with processing electrical equipment are minimized by sampling the discrete coordinates for a particular point over an integral number of cycles of the power line frequency.

Abstract: A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising first and second signal level storage means each having first input means responsive to the first and second input signals, respectively, first output means, and clock input means and responsive to a clock signal supplied to the clock input means to cause the logic level on its output means to become equal to the logic level on its first input means. First and second Exclusive OR gates each have a first input means connected respectively to said first input means of said first and second signal level storage means, and a second input means connected respectively to said first output means of said first and second signal level storage means.

Abstract: Analog-to-digital conversion through successive approximation is implemented by means of a charge coupled device. During the conversion process two charges are compared, each comparison yielding one bit of a multi-bit number. By increasing the lesser of the compared charges after each comparison, the need to subtract charge as part of the successive approximation process is eliminated.

Abstract: Combining integrated injection logic (I.sup.2 L) and linear circuitry permits fabrication of a highly dense analog-to-digital (A-to-D) converter. The heart of the A-to-D converter is a linear-I.sup.2 L plurality of high density variable current sources which are proportional to each other. These variable current sources, when used in combination with I.sup.2 L constant current sources and current sensing means, provide a highly compact A-to-D converter.

Abstract: An electronic switch for converting a pulse signal into a continuous analog signal by connecting a d.c. voltage to an integrating circuit under the control of pulses of the pulse signal comprising two switching elements connected by a voltage divider, and lying between the poles of the d.c. voltage source, the divider ratio being selected to compensate the effects on the analog output signal at the output of the integrating circuit of temperature dependence of the switching elements.

Abstract: A control circuit for a continuous conversion of information carrying anaous voltage and current signals into digital magnitudes containing said information, the respective digital magnitude is so coded that always one digital magnitude differs from the next higher digital magnitude merely by a one-digit digital information value. The circuit of the invention is characterized primarily in that for a simultaneous reception of the signals there are provided one or more serially arranged analogous digital converters as well as control stages comprising one or more groups, while the groups for folding the signals are formed by differential converters which emit the folded signals at the exit of the respective group and while an analogous digital converter follows the control stage or stages. The analogous digital converter forms informational values of the digital magnitudes by a subdivision of the signals.

Abstract: A waveform digitizer particularly suitable for use in electronic test systems for analyzing and displaying analog signals is disclosed. A digitally derived reference voltage is compared with the analog signal to be digitized during a series of comparison sequences. Simultaneously with the start of each comparison sequence a digital clock is started. Each time the analog signal rises above, or drops below, the reference voltage a decision change detector produces an enable pulse. Each time an enable pulse occurs, a data word, having a portion related to the value of the digitally derived reference voltage and a portion related to the digital clock value, is stored and/or used to control a display. At the end of the first comparison sequence (determined when the digital clock value reaches a predetermined level) the reference voltage is incremented and a second comparison sequence started. These steps are repeated until the reference voltage reaches a predetermined level.

Abstract: An MOS, integrated circuit, analog-to-digital converter powered by a single power supply potential and suitable for converting an analog signal equal to that power supply potential is described. The input analog signal is capacitively divided by two; resistor strings interlaced with the resistance ladder of the digital-to-analog converter provides a reduced reference potential. A chopper amplifier is employed in the comparator which includes circuits for reducing offset potentials.

Abstract: A reversible analog to digital converter is designed for high precision in the interrelation of analog voltages and binary digital representations. An upper and a lower limit voltage converge on the analog voltage level in binarily decreasing steps. The upper and lower limits are averaged to form a trial voltage; in A/D conversion the trial voltage replaces one of the limits in accordance with a comparison between the analog voltage and the trial voltage, in digital to analog conversion the trial voltage replaces one of the limits in accordance with a binary input signal.

Abstract: An analog signal is sampled in response to a sampling command. Each time that the analog signal, or the difference between the analog signal and the previous sample thereof, crosses a respective reference level, a digital signal is produced. Each digital signal consists of a code representing the level crossing or incremental change in level which has occurred and a count representing the time which has elapsed since the last sample command. A digital signal is also produced if the elapsed time reaches a predetermined period. On production of each digital signal, a sampling command is produced and the elapsed time counting is recommenced. The digital signals constitute a digital representation of the analog signal. The converter is particularly useful for converting analog signals having both very high and very low frequency portions, such as current surges which occur on telephone lines affected by lightning (high frequency) and 60 Hz induction (low frequency).

Abstract: A bucket brigade A/D weighting function multiplier which provides a simultaneous A/D conversion and multiplication by a weighting function in a continuous pipe line fashion, is disclosed. Each converted bit from the A/D converter is utilized by the multiplier as it becomes available instead of waiting for the conversion of the entire word, to provide a weighted digital output.

Abstract: An electronic circuit is described for providing an analog-to-digital conversion system having an output "delta" format in which a pulse is produced for each defined change in the amplitude of the input signal. The circuit is characterized by minimal hardware complexity and low current drain. In performing its conversion function, the circuit advantageously employs a single capacitor for coupling the input signal into the system as well as for storing precisely controlled voltage increments for effecting the equality of the input signal and a reference potential. The AC coupling afforded by this configuration eliminates the problems attendant with the digitization of a small AC signal superimposed on a large DC component. Additionally, the circuit of the present invention lends itself to the multiplexing of input signals.

Abstract: A device for reducing irrational-base codes to a minimal form, comprising "n" identical functional cells whereof each Bth cell incorporates a flip-flop with a count input and an AND convolution element intended to evaluate the possibility of performing the operation of convoluting the (B-1)th and (B-p-1)th code digits to the Bth code digit. One of the inputs of the AND convolution element is connected to an inverting output of the flip-flop whose direct output serves as an information output of the Bth functional cell. The flip-flop has its set, reset and count inputs connected to an information input, a convolution set input and an inversion signal input, respectively, of the Bth functional cell, the inversion signal input being connected to an information output of the (B-1)th functional cell. The remaining inputs of the AND convolution element are a first convolution signal input, a second convolution signal input and a convolution control input of the Bth functional cell.

Abstract: A digital-analog converter comprises a reference value adder having its multidigit input coupled to a multidigit output of a switch unit and a Fibonacci p-code convolution unit. The fibonacci p-code convolution unit has its multidigit output coupled to a multidigit input of the switch unit. The Fibonacci p-code convolution unit comprises n stages, each of which, related to a certain bit position in a range from one to n-2, comprises an AND gate and an OR gate. Each of the stages corresponding to bit positions from zero to n-1 comprises a flip-flop, an OR gate and an AND gate. The set and reset inputs of the flip-flop of each stage are coupled, respectively, to the output of the AND gate and to the output of the OR gate. The set input of the flip-flop of the stage of the zero bit position is a counting input of the digital-analog converter. First and second inputs of the OR gate of the stage of the ith bit position are coupled, respectively, to the outputs of the AND gates of the (i+l)th and (i+p+l)th states.

Abstract: A waveform acquisition circuit for both real-time and equivalent-time acquisition modes with a smooth transition between modes. The circuit includes a control circuit which causes an analog-to-digital converter to take samples of an analog waveform in precise time relationship with preselected data points along the time axis of the waveform. The data points may be preselected in accordance with a variable increment.

Abstract: A new encoder for an analog to digital converter of the successive approximation type incorporates instrumentation amplifier and signal sample and hold functions within the encoder proper, thereby substantially simplifying the converter circuitry. An input analog current signal is applied to a sample and hold capacitor within the encoder through the encoder comparator at a time when the weighted reference signal to the comparator is set to zero. The capacitor stored analog voltage is subsequently applied to the encoder summing node and the encoding sequence ensues. The encoder may be provided with offset and gain correction circuitry, conventionally found exterior to the encoder. In one embodiment of the invention, offset correction is effected using the signal sample and hold capacitor.

Abstract: In a dual-slope A/D converter employing hysteresis, a reference voltage circuit sets the threshold of the comparator at three distinct levels in response to a ramp control signal and the comparator output. As a reference capacitor ramps through a threshold voltage, the comparator output shifts the threshold with positive feedback (hysteresis) to provide noise immunity. The ramp control signal then shifts the threshold back to its original level cancelling the hysteresis provided at the first comparator trip point. Thus, the comparator switches at the same voltage for both slopes eliminating offset error.

Abstract: A signal to be quantized is translated to a charge Q and the latter is multiplied by a fraction f to produce a fractional charge packet fQ. Then, another fractional charge packet is produced by multiplying the remainder Q(1-f) of the charge packet by f. This last step is repeated for succeeding remainder charge packets a sufficient number of times until a total of n-1 fractional charge packets have been produced, where n is the number of quantization levels desired. The successive fractional charge packets are compared with threshold levels of different amplitudes to determine the number of incremental charge packets, each of the same size, to be added to one another to form a quantized charge packet.