Abstract: A semiconductor device including a first oxide including a first region and a second region adjacent to each other and a third region and a fourth region with the first region and the second region sandwiched between the third region and the fourth region, a second oxide over the first region, a first insulator over the second oxide, a first conductor over the first insulator, a second insulator over the second oxide and on side surfaces of the first insulator and the first conductor, a third insulator over the second region and on a side surface of the second insulator, a second conductor over the second region with the third insulator positioned between the second region and the second conductor and on the side surface of the second insulator with the third insulator positioned between the side surface of the second insulator and the second conductor, and a fourth insulator covering the first oxide, the second oxide, the first insulator, the first conductor, the second insulator, the third insulator, and th

Abstract: The present invention relates to: a method for manufacturing a transparent light emitting device, which can minimize the manufacturing time of a large-area high-resolution transparent light emitting device and maximize the productivity thereof by forming an integrated metal mesh circuit pattern through a UV imprinting technology; and a transparent light emitting device manufactured thereby.

Abstract: A semiconductor device includes a buried dielectric layer, a first gate structure, a second gate structure, a first source/drain region, a second source/drain region, a first contact structure and a second contact structure. The first gate structure and the second gate structure disposed respectively in the front-side and backside of the dielectric layer, the first source/drain region and the second source/drain region are disposed between the first gate structure and the second gate structure, the first contact structure is disposed in the front-side of the dielectric layer and electrically coupled to the first source/drain region, the second contact structure is disposed in the backside of the dielectric layer and electrically coupled to the second source/drain region.

Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.

Abstract: An apparatus and a method are provided for selectively and rapidly applying heat to a nanoscale environment in a controlled manner. The technology utilizes laser irradiation of a solid state material to heat a nanoscale point of interest by an optothermal effect. The technology can be used to the tip of an atomic force microscope, a spot on a flat surface, or a nanopore, or molecules in their vicinity. The apparatus and method are capable of rapidly scanning the temperature of a nanoscale object such as a molecule or biomolecular complex and to interrogate properties of the object at high throughput. The methods can be used in nanofabrication processes or to drive single molecule chemistry.

Abstract: An array substrate and a method of manufacturing the same are provided. The array substrate sequentially includes a flexible substrate, a buffer layer, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an inter-insulating layer, a first organic filling layer, a source-drain wiring layer, a planarization layer, an anode layer, a pixel defining layer, and a supporting layer from bottom to top; the first organic filling layer is convex upward on the inter-insulating layer, making the source-drain wiring layer covering thereon disposed to be convex. The method of manufacturing the array, substrate is sequentially to manufacture the layers from bottom to top, wherein the convex first organic filling layer disposed on the inter-insulating layer of the array substrate is used to raise a drain thereon.

Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.

Abstract: Techniques to facilitate protection of control system content used in an industrial automation environment are disclosed herein. In at least one implementation, the control system content for use in the industrial automation environment is received, wherein the control system content comprises controller program code that directs an industrial controller to drive a machine system. Content protection instructions for the control system content are also received, wherein the content protection instructions comprise restrictions on execution of the control system content. An execution license that includes process-related constraints for the control system content is generated based on the content protection instructions. The execution license is applied to the control system content to generate protected content, wherein use of the control system content is granted subject to the process-related constraints of the execution license.

Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.

Abstract: A method is presented for forming a wrap-around-contact. The method includes forming a bottom source/drain region adjacent a plurality of fins, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, and for forming top spacers adjacent the top portions of the plurality of fins. The method further includes disposing a sacrificial liner adjacent the encapsulation layers, recessing the top spacers, forming top source/drain regions over the top portions of the plurality of fins, removing the sacrificial liner to create trenches adjacent the top source/drain regions, and depositing a metal liner within the trenches and over the top source/drain regions such that the wrap-around-contact is defined to cover an upper area of the top source/drain regions.

Abstract: A flexible display panel is provided and defined with a special-shaped cutout area and a display area, including a substrate, and a plurality of pixel structures, a scan line layer, and a data line layer disposed above the substrate, wherein each of the plurality of the pixel structures includes three sub-pixels, and the scan line layer includes a plurality of scan lines, and the data line layer includes a plurality of data lines. The sub-pixels are arranged as an array over the substrate, and the scan lines and the data lines are disposed in the array of the sub-pixels. A scan line is disposed between every two rows of the sub-pixels and two data lines are disposed between every column of the sub-pixels in the special-shaped cutout area. Therefore, the frame of the special-shaped cutout area can be reduced to realize the narrow frame of the special-shaped cutout area.

Abstract: Provided is a production method for a magnetoresistive element including treating a stacked layer into a predetermined shape. The stacked layer includes a magnetoresistive layer whose resistance changes depending on a magnetic field and a cap layer above the magnetoresistive layer and having a thickness in a range of 10 nm to 60 nm. The method further includes covering and protecting the stacked layer with an insulating layer, forming an opening in the insulating layer by reactive etching and exposing a surface of the cap layer at the opening, etching the cap layer in a range less than a total thickness of the cap layer by ion milling of the surface, and depositing an upper layer to be a part of the magnetoresistive element. The upper layer is in contact with the surface of the cap layer after the etching.

Abstract: The semiconductor device including a substrate comprising a chip region and a guard-ring region which surrounds a side surface of the chip region, an isolation layer configured to define an active region within the guard-ring region, a first doping layer in the active region and doped with first impurities having a first doping concentration, a second doping layer on the first doping layer and in the active region, the second doping layer doped with second impurities having a same conductivity type as the first impurities of the first doping layer, the second impurities having a second doping concentration, the second doping concentration being greater than the first doping concentration, a first gate electrode on the second doping layer, and a first wire layer on the first gate electrode may be provided.

Abstract: A packaged electronic device includes a package structure that encloses first and second semiconductor dies, a die attach pad with a first side attached to one of the dies, and a second side exposed along a side of the package structure, and a substrate that includes a first metal layer exposed along another side of the package structure, a second metal layer soldered to contacts of the dies, and an isolator layer that extends between and separates the first and second metal layers.

Abstract: A display panel is provided, which includes a substrate, multiple light emitting structures arranged in an array on the substrate, a blocking structure at least arranged in a peripheral region of the substrate, and a cathode layer arranged on the multiple light emitting structures and the blocking structure. The cathode layer is discontinuous at a location corresponding to the blocking structure.

Abstract: A method for forming a fin field effect transistor device structure includes forming fin structures over a substrate. The method also includes forming a gate structure across the fin structures. The method also includes forming source/drain epitaxial structures over the fin structures. The method also includes forming blocking structures between the source/drain epitaxial structures. The method also includes depositing contact structures over the source/drain epitaxial structures and between the blocking structures. The method also includes removing a top portion of the blocking structures. The method also includes depositing an etch stop layer over the blocking structures and the contact structures, so that an air gap is formed between the etch stop layer and the blocking structure.

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

Abstract: A three-dimensional (3D) semiconductor device includes a substrate having a cell array region and a peripheral circuit region. A cell array structure is in the cell array region and includes a 3D memory cell array. A peripheral logic structure is in the peripheral circuit region and includes a peripheral circuit transistor. A cell insulating layer insulates the cell array structure. A peripheral insulating layer is insulated from the peripheral logic structure and the cell array region and has a porous layer.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a source, a drain, a gate structure, and a first p-type doped III-V compound/nitride semiconductor layer. The second semiconductor layer is disposed on the first semiconductor layer and has a bandgap greater than a bandgap of the first semiconductor layer. The source and the drain are disposed on the second semiconductor layer. The gate structure is disposed on the second semiconductor layer and between the source and the drain. The first p-type doped III-V/nitride semiconductor compound layer is disposed on the second semiconductor layer and between the gate structure and the drain with the drain at least partially covering the p-doped layer such that the first p-type doped III-V compound/nitride semiconductor layer and the drain are electrically coupled with each other.

Abstract: A method is presented for limiting lateral protrusion of neighboring epitaxial growths. The method includes masking an n-type field effect transistor (NFET) region of a semiconductor substrate with a first mask, forming first epitaxial source/drain regions in a p-type field effect transistor (PFET) region, where the first mask limits lateral growth of the first epitaxial source/drain regions in the PFET region toward the NFET region, masking the PFET region of the semiconductor substrate with a second mask, and forming second epitaxial source/drain regions in the NFET region, where the second mask limits lateral growth of the second epitaxial source/drain regions in the NFET region toward the PFET region.