Patents Examined by Thomas M. Heckler
  • Patent number: 6748527
    Abstract: A command fetch control section 1 has an address selection function of selecting the start address of an initialization program stored in a local memory (RAM 6) or an external memory (ROM 9) connected through external buses 7 and 8, based on an address selection signal MS externally given. When a processor 10 in which one or both of the supplies of its internal clocks bck and cck have been stopped after the system wad powered on, is to be restarted, the processor 10 can read out the initialization program necessary for its restarting operation from the high-speed RAM 6. Thus the restarting operation can be performed rapidly.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: June 8, 2004
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Utsumi, Yoshio Hirose
  • Patent number: 6745369
    Abstract: A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: June 1, 2004
    Assignee: Altera Corporation
    Inventors: Roger May, James Tyson, Edward Flaherty, Mark Dickinson
  • Patent number: 6738918
    Abstract: One memory controller and a plurality of memory modules are connected to a data bus line, clock bus line, and command bus line. Each memory module includes an internal clock signal generating circuit for generating internal clocks synchronizing with external clock signals output from the memory controller. This internal clock signal generating circuit has a function of adjusting the timing of a generated internal clock signal on the basis of a control signal in accordance with the position on the bus lines of a memory module having this internal clock signal generating circuit.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: May 18, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Patent number: 6735709
    Abstract: An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: May 11, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Terry R. Lee, Kevin J. Ryan, Joseph M. Jeddeloh
  • Patent number: 6735708
    Abstract: A portable system is provided with both an ISPCA processing section, a non-standard personal computer architecture (NSPCA) processing section and a common section including apparatus common to both processing sections. The NSPCA processing section operates under an operating system such as the WINDOWS® CE operating system, having reduced functionality, but being capable of “instant-on” operation. The data processing system includes controllable reduced power (and reduced functionality) mode wherein only the NSPCA processing is activated. The data processing system can controllably be transferred to a higher power (and full functionality) mode operating by activating the ISPCA processing section. In this manner, the processing section that is not an integral part of the data processing system can be detachably coupled thereto.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: May 11, 2004
    Assignee: Dell USA, L.P.
    Inventor: La Vaughn F. Watts, Jr.
  • Patent number: 6735706
    Abstract: A programmable power management integrated circuit includes analog input monitors that receive analog input signals that correspond to voltage, current, or temperature measurements. The analog input monitors apply programmable thresholds to the measurements and output the results to a programmable logic device, which may generate various status and/or control signals to the system being monitored. The programmable logic device controls FET drivers that can switch on and off power to the monitored system. The programmable power management integrated circuit may also comprise an internal oscillator, a serial interface, an in-system programmable interface, a joint test action group interface, a memory that stores identification information, and a register for capturing system information during power-down.
    Type: Grant
    Filed: December 6, 2000
    Date of Patent: May 11, 2004
    Assignee: Lattice Semiconductor Corporation
    Inventors: Jock F. Tomlinson, David C. Wilkinson, James J. Bennett, Douglas C. Morse
  • Patent number: 6732286
    Abstract: A phase locked loop circuit, including a digital filter loop for timing recovery, includes a phase synchronization feedback loop, a frequency synchronization feedback loop, and a phase shift measurement circuit. The phase shift measurement circuit includes a shift register. Timing recovery takes place by first operating the circuit in an acquisition mode, then operating the circuit in a tracking mode. During the acquisition mode, an input to the frequency synchronization feedback loop is set to zero, and the phase synchronization feedback loop is operable at a high bandwidth rate to synchronize phase and to compute a value of frequency offset using the shift register. During the tracking mode, the input to the frequency synchronization feedback loop is set equal to the computed value of frequency offset.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 4, 2004
    Assignee: Marvell International, Ltd.
    Inventor: Pantas Sutardja
  • Patent number: 6732268
    Abstract: A first aspect of the present invention is a method controlling an orientation-dependent component in a computer system. The method comprises the steps of interpreting a signal, the signal being based on an orientation of the computer system and automatically reconfiguring the orientation-dependent component based on the interpretation of the signal. A second aspect of the present invention is a system for controlling an orientation-dependent component in a computer system. The system comprises means for interpreting a signal, the signal being based on an orientation of the computer system and means for automatically reconfiguring the orientation-dependent component based on the interpretation of the signal. Through the use of the method and system in accordance with the present invention, orientation-dependent components are automatically reconfigured when a computer is changed from a rack orientation to a tower orientation (or vice versa) without having to manually adjust the settings of the components.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: May 4, 2004
    Assignee: International Business Machines Corporation
    Inventors: Robert Joseph Christopher, William Craig Troop
  • Patent number: 6732264
    Abstract: Firmware for a computer system reduces boot time utilizing the multi-tasking capabilities of a processor to perform at least two boot tasks simultaneously. The boot tasks can be divided into groups which are executed in parallel. To accommodate certain boot tasks which must be performed in sequence, the boot tasks can be arranged in groups which are executed sequentially. The tasks within each group are performed simultaneously. The boot time is also reduced by only enumerating hardware if the system hardware has been changed since the previous boot. The firmware determines if hardware has been changed by checking an electrical hardware latch which signals whether the computer case has been opened.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: May 4, 2004
    Assignee: Intel Corporation
    Inventors: Jiming Sun, Albert Tsang
  • Patent number: 6728890
    Abstract: A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: April 27, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Russell N. Mirov, Michel Cekleov, Mark Young, William M. Baldwin
  • Patent number: 6725367
    Abstract: A configuration system is disclosed that applies rules of precedence to evaluate parameters in the context of multiple sections within a configuration file and in the context of multiple configuration files. The system brings together multiple sections and multiple files into a unified whole. The precedential order of sections and files is set by a user and special section names can be used to override default precedential rules. If a parameter is set multiple times at different levels in the hierarchy of belonging, its final value reflects the value set at the level most closely concerned with the setting of the parameter. The value of a parameter can be set from an environmental variable or from the value of another parameter. If a parameter's value depends upon the value of another parameter, that second parameter is recursively evaluated using the same precedential rules.
    Type: Grant
    Filed: January 29, 2001
    Date of Patent: April 20, 2004
    Assignee: Microsoft Corporation
    Inventors: Conor P. Morrison, Sivaprasad V. Padisetty
  • Patent number: 6725386
    Abstract: A method for causing a host channel adaptor which is involved with a clustered arrangement to hibernate. Before the HCA can hibernate, it is necessary for its clients to hibernate first. Once this is accomplished, all data is stored in memory and the HCA goes into hibernation. It resumes operation when a request is received. The HCA is checked to see if it has been changed and various parameters are examined to determine if an error has occurred which is unrecoverable. If not, the operation of the device is resumed.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: April 20, 2004
    Assignee: Intel Corporation
    Inventor: Rajesh R. Shah
  • Patent number: 6721880
    Abstract: A method and apparatus are disclosed for maintaining and distributing configuration information for a given service by the configured service itself. The configured service controls the creation of its own configuration information, as well as updates and access thereto. Any valid and authorized updates to the configuration information may be implemented by the configured service immediately. The configured service can maintain the configuration information as a synthetic file in a hierarchical file system, for access by authorized end-users (clients). The information recorded in the configuration file can be presented, maintained and updated in the same manner as a dynamic file. Access control features of the file system can be utilized to restrict access to the configuration files and the editing tools can be used to update the configuration information. All end-users can access the same configuration information using the same dynamic file.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: April 13, 2004
    Assignee: Lucent Technologies Inc.
    Inventor: Robert Pike
  • Patent number: 6721879
    Abstract: In a case where maintenance operations are sequentially performed while the status of a computer peripheral device is determined, the status of the computer peripheral device may not be clearly determined, and it may be difficult for a user to perform the next operation. In a setup operation of a printer 1050, the status of the printer 1050 such as existence/absence of ink cartridge or ink charging operation is detected on the side of computer 1010 via a printer driver 1073. On the other hand, a setup guide program 1075 determines the progress of the setup operation from the status change of the printer 1050, and sequentially displays images showing operation procedures in correspondence with the progress. Accordingly, it is not necessary for the user to perform the setup operation while determining the status of the printer 1050, and the user can smoothly perform the setup operation.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: April 13, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Shinji Tanaka
  • Patent number: 6718474
    Abstract: A method and apparatus for controlling processor clock rates of a synchronous multi-processor system in response to an environmental condition of a processor. In one embodiment, a processor-reported an environmental condition is stored in a register and all processors are interrupted simultaneously. Upon interrupt, each processor reads the contents of the register and responds by adjusting its local clock rate synchronously with the other processors. In another embodiment, the processor's environmental status is polled by software control. Upon notification of an environmental condition, the software control notifies each processor to adjust its local clock rate synchronously with the other processors.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: April 6, 2004
    Assignee: Stratus Technologies Bermuda LTD.
    Inventors: Jeffrey Somers, Kurt Thaller, Nicholas Warchol
  • Patent number: 6718464
    Abstract: A method and system are disclosed for dynamically loading selected BIOS modules and settings from a server computer system to a client computer system according to an identity of a user who is currently utilizing the client computer system. The client computer system is coupled to a server computer system via a network. Selected BIOS modules and settings are associated with a particular user. These BIOS modules and settings are those preferred by the particular user to use in order to customize the client computer system when the client computer system is used by the particular user. The associations among the particular user and the selected BIOS modules and settings are stored in the server computer system. The selected BIOS modules and settings are downloaded from the server computer system to the client computer system when the particular user causes the client computer system to start booting, i.e. when the particular user is the current user.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: April 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Daryl Carvis Cromer, Eric Richard Kern, Howard Jeffrey Locker, David Rhoades, James Peter Ward
  • Patent number: 6715131
    Abstract: Techniques that facilitate participation of mobile devices in accessing resources over a data network are disclosed. The data network can be wired, wireless or some combination thereof. In one aspect, a mobile navigation metaphor is provided to yield similar navigation experiences on both mobile devices and personal computers. In another aspect, a central content server is able to return requested content to requesters in a format suitable for their device.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: March 30, 2004
    Assignee: Openwave Systems Inc.
    Inventors: Bruce K. Martin, Jr., Arnaud P. Y. Capitant, Lawrence M. Stein, Jonathan M. Wulff, Andrew L. Laursen
  • Patent number: 6715017
    Abstract: An interruption signal generating apparatus comprises a counter unit counting a predetermined time interval and outputting a count-up signal indicating the end of the counting; a first generating unit detecting the end of the counting indicated by the count-up signal and generating a first interruption signal indicating the detection according to a first clock; a second generating unit detecting the end of the counting indicated by the count-up signal and generating a second interruption signal indicating the detection according to a second clock; and a selecting unit selectively outputting the first and second interruption signals. Even in the stop mode in which a bus clock for making the computer system operative is unprovided, the interruption signal can be generated in a manner similar to the normal mode in which the bus clock is provided.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: March 30, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kazunari Sesumi
  • Patent number: 6715089
    Abstract: A computer system has at least one processor and at least one queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of rates. A number of instructions in the queue is measured. The optimum clock rate is selected based on in part the determined number of queued instructions.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: March 30, 2004
    Assignee: ATI International SRL
    Inventor: Andrej Zdravkovic
  • Patent number: 6711615
    Abstract: A method of network surveillance includes receiving network packets handled by a network entity and building at least one long-term and a least one short-term statistical profile from a measure of the network packets that monitors data transfers, errors, or network connections. A comparison of the statistical profiles is used to determine whether the difference between the statistical profiles indicates suspicious network activity.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: March 23, 2004
    Assignee: SRI International
    Inventors: Phillip Andrew Porras, Alfonso Valdes