Abstract: An object is to provide a plasma processing device capable of rightly monitoring existence of plasma discharge and also rightly monitoring existence of abnormal discharge. Another object of the present invention is to provide a method of monitoring a state of plasma discharge in the plasma processing device. A discharge detection sensor 23, in which a dielectric member 21 and a probe electrode unit 22 are combined with each other, is attached to an opening portion 2a provided in a lid portion 2 composing a vacuum chamber.
Abstract: According to one embodiment, a method for manufacturing a template for imprinting includes preparing a first template having a device pattern and a plurality of identification patterns, and forming a second template by transferring the device pattern and at lest desired one of the identification patterns to a template substrate.
Abstract: The present invention relates to a method and an arrangement for restoring strength and wear resistant of a metallic matrix ceramic (1) comprising a metallic binder (2) and ceramic filler (3) particles, which metallic matrix ceramic (1) has been exposed for long term high temperature and pressure cycling, for example in a gas exhaust nozzle (6), whereby micro cracks (4) are developed in the outer layer (5) of the metallic binder (2) According to the invention this is achieved by virtue of the fact that the outer layer (5) of the metallic binder (2), partly or fully, is removed from the MMC part (1) by a chemical operation, where after the outer layer (5) is compressed by a compression operation for achieving a dense outer layer (5), in which filler (3) particles are close to each other.
Abstract: A method for combinatorially processing a substrate is provided. The method includes introducing a first etchant into a reactor cell and introducing a fluid into the reactor cell while the first etchant remains in the reactor cell. After initiating the introducing the fluid, contents of the reactor cell are removed through a first removal line and a second removal line, wherein the first removal line extends farther into the reactor cell than the second removal line. A level of the fluid above an inlet to the first removal line is maintained while removing the contents. A second etchant is introduced into the reactor cell while removing the contents through the first removal line and the second removal line. The method includes continuing the introducing of the second etchant until a concentration of the second etchant is at a desired level, wherein the surface of the substrate remains submerged.
Abstract: The invention relates to a gear train (51, 51?) including an arbour (53, 53?) a first end of which is fitted with an integral collar (52, 52?), a first wheel set (55, 55?) made of micro-machinable material being fitted onto the second end of the arbour (53, 53?). According to the invention, the gear train (51, 51?) includes a second wheel set (57, 57?) made of micro-machinable material, which is independent of the movements of said first wheel set and which includes an aperture (58, 58?) whose wall is mounted opposite said arbour so that the second wheel set (57, 57?) is freely mounted on said first end of the arbour (53, 53?).
Abstract: A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum or tungsten layer on a TiN layer on an HfO2 or ZrO2 layer on a silicon substrate. In some embodiments, the method comprises a physical sputter process to selectively etch the platinum layer, followed by a first wet etch using a mixture of NH4OH and H2O2 to selectively etch the TiN layer, and a second wet etch using a dilute mixture of HF and HCl to selectively etch the HfO2 or ZrO2 layer.
Type:
Grant
Filed:
November 29, 2011
Date of Patent:
December 24, 2013
Assignee:
Intermolecular, Inc.
Inventors:
Jinhong Tong, Frederick Fulgenico, ShouQian Shao
Abstract: Provided is a method for manufacturing a multilayer wiring board, whereby even if the multilayer wiring board suffers warping or irregularities, thin-film patterns with great uniformity that are to be used as a mask for forming a wiring layer can be obtained in a simple way. A primer-coated metal foil 20 composed of a primer resin layer 21 and a metal layer 22 is placed on a surface of a double-face CCL 10, which is prepared by applying metal layers 12 and 13 onto the surfaces of a support base 11, and the primer-coated metal foil 20 and the double-face CCL 10 are bonded and the primer resin layer 21 is cured. A via Vb is thereafter formed from the metal layer 22 side, and a metal-plate layer 30 is formed on the resulting metal layer 22. After that, the etched down metal-plate layer 30 and the metal layer 22 are patterned, and using the patterned layers as a mask, the primer resin layer 21 is patterned.
Abstract: A chemical mechanical polishing composition is provided, comprising, as initial components: water, an abrasive; a diquaternary substance according to formula (I); a derivative of guanidine according to formula (II); and, optionally, a quaternary ammonium salt. Also, provided is a method for chemical mechanical polishing of a substrate, comprising: providing a substrate, wherein the substrate comprises silicon dioxide; providing the chemical mechanical polishing composition of the present invention; providing a chemical mechanical polishing pad; creating dynamic contact at an interface between the chemical mechanical polishing pad and the substrate; and dispensing the chemical mechanical polishing composition onto the chemical mechanical polishing pad at or near the interface between the chemical mechanical polishing pad and the substrate; wherein the chemical mechanical polishing composition has a pH of 2 to 6.
Type:
Grant
Filed:
September 20, 2010
Date of Patent:
October 29, 2013
Assignee:
Rohm and Haas Electronic Materials CMP Holdings, Inc.
Inventors:
Zhendong Liu, Yi Guo, Kancharla-Arun Kumar Reddy, Guangyun Zhang
Abstract: The invention relates to compositions and methods that are useful in etching a metal surface. In particular, the invention relates to novel acid compositions and methods of using such compositions in etching a metal surface, preferably an aluminum surface prior to anodizing to dissolve impurities, imperfections, scale, and oxide. The compositions are effective in maintaining their etching capacity and in removing smut produced by the etching of a surface as well as in general cleaning.
Abstract: According to a disclosed semiconductor device fabrication method according to one embodiment of the present invention, a layer having a line-and-space pattern extending in one direction is etched using another layer having a line-and-space pattern extending in another direction intersecting the one direction, thereby obtaining a mask having two-dimensionally arranged dots. An underlying layer is etched using the mask, thereby providing two-dimensionally arranged pillars.
Type:
Grant
Filed:
November 23, 2009
Date of Patent:
August 27, 2013
Assignees:
Tokyo Electron Limited, Tohoku University
Abstract: A method of fabricating a c-aperture or E-antenna plasmonic near field source for thermal assisted recording applications in hard disk drives is disclosed. A c-aperture or E-antenna is built for recording head applications. The technique employs e-beam lithography, partial reactive ion etching and metal refill to build the c-apertures. This process strategy has the advantage over other techniques in the self-alignment of the c-aperture notch to the c-aperture internal diameter, the small number of process steps required, and the precise and consistent shape of the c-aperture notch itself.
Type:
Grant
Filed:
November 29, 2011
Date of Patent:
July 16, 2013
Assignee:
HGST Netherlands B.V.
Inventors:
Hamid Balamane, Thomas Dudley Boone, Jordan Asher Katine, Barry Cushing Stipe
Abstract: A producing method of a wired circuit board includes a laminating step of preparing a metal supporting board, forming an insulating base layer on the metal supporting board, forming a conductive layer including a terminal portion and a plating lead continued from the terminal portion on the insulating base layer, and forming an insulating cover layer on the insulating base layer so as to cover the conductive layer, a first etching step of etching the metal supporting board, and then etching the insulating base layer to expose the plating lead from the metal supporting board and the insulating base layer, and a second etching step of etching the exposed plating lead.
Abstract: According to one embodiment, a method of manufacturing a magnetic recording medium comprises forming a protective film on a ferromagnetic recording layer containing Cobalt (Co) on a substrate and forming a recess in both the protective film and the ferromagnetic recording layer at a part where a nonmagnetic layer is to be formed. The method further comprises removing Co from a part of the recess of the ferromagnetic recording layer to form the nonmagnetic layer that separates magnetic patterns made of the ferromagnetic recording layer containing Co. The nonmagnetic layer has an identical chemical composition as the ferromagnetic recording layer, except for the nonmagnetic layer having a lower Co concentration than the magnetic patterns.
Abstract: An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the showerhead electrode.
Type:
Grant
Filed:
September 17, 2010
Date of Patent:
April 16, 2013
Assignee:
Lam Research Corporation
Inventors:
Gregory R. Bettencourt, Gautam Bhattacharyya, Simon Gosselin Eng., Sandy Chao, Anthony de la Llera, Pratik Mankidy
Abstract: A resist layer is formed over one surface of a current-collector material, while a resist layer having a predetermined pattern is formed on the other surface of the current-collector material. Through-holes are formed on the current-collector material through an etching process. An electrode slurry is applied onto the current-collector material formed with the through-holes without removing the resist layers. Specifically, since the through-holes are closed by the resist layer, the electrode slurry does not pass through the through-holes to leak out. Therefore, the current-collector material can be conveyed in the horizontal direction, whereby the productivity of an electrode can be enhanced. The resist layers are made of PVdF, and the resist layers are removed in a heating and drying step in which the PVdF is dissolved.
Abstract: Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern.
Type:
Grant
Filed:
October 19, 2009
Date of Patent:
January 29, 2013
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Bong-cheol Kim, Dae-youp Lee, Hyun-woo Kim, Young-moon Choi, Jong-su Park, Byeong-hwan Son
Abstract: A lithography mask includes a plurality of patterning features formed on a mask substrate and a first plurality of sub-resolution assist features (SRAFs) formed substantially perpendicular to the patterning features on the mask substrate.
Abstract: A method for manufacturing a magnetic write head having a write pole with a tapered trailing edge step. The resulting tapered trailing edge step maximizes write field at very small bit sizes by preventing the magnetic saturation of the write pole at the pole tip. The method includes depositing a magnetic write pole material and then depositing a magnetic material over the magnetic write pole material. A RIE mask and hard mask are deposited over the magnetic bump material. A resist mask is formed over the RIE mask and hard mask, and a reactive ion etching is performed to transfer the pattern of the resist mask onto the underlying hard mask. Then an ion milling is performed to form a the magnetic step layer with a tapered edge that defines a tapered trailing edge step structure of the write pole.
Type:
Grant
Filed:
December 24, 2008
Date of Patent:
August 28, 2012
Assignee:
Hitachi Global Storage Technologies Netherlands B.V.
Inventors:
Aron Pentek, Sue Siyang Zhang, Yi Zheng
Abstract: A composition and associated method for chemical mechanical planarization of a metal-containing substrate afford low dishing levels in the polished substrate while simultaneously affording high metal removal rates. Suitable metal-containing substrates include tungsten- and copper-containing substrates. Components in the composition include a silatrane compound, an abrasive, and, optionally, a strong oxidizing agent, such as a per-compound.
Abstract: A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.
Type:
Grant
Filed:
June 16, 2008
Date of Patent:
April 17, 2012
Assignee:
International Business Machines Corporation
Inventors:
Wu-Song Huang, Wai-kin Li, Ping-Chuan Wang