Patents Examined by Thomas T Pham
  • Patent number: 11651969
    Abstract: An etching method according to one embodiment, includes alternately switching a first step and a second step. The first step introduces a first gas containing a fluorine atom without supplying radiofrequency voltage to form a surface layer on a surface of a target cooled at a temperature equal to or lower than a liquefaction temperature of the first gas. The second step introduces a second gas gaseous at the first temperature and different from the first gas, and supplies the radiofrequency voltage, to generate plasma from the second gas to etch the target by sputtering using the plasma.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: May 16, 2023
    Assignee: Kioxia Corporation
    Inventors: Chihiro Abe, Toshiyuki Sasaki, Hisataka Hayashi, Mitsuhiro Omura, Tsubasa Imamura
  • Patent number: 11643728
    Abstract: Vapor deposition methods for depositing transition metal dichalcogenide (TMDC) films, such as rhenium sulfide thin films, are provided. In some embodiments TMDC thin films are deposited using a deposition cycle in which a substrate in a reaction space is alternately and sequentially contacted with a vapor phase transition metal precursor, such as a transition metal halide, a reactant comprising a reducing agent, such as NH3 and a chalcogenide precursor. In some embodiments rhenium sulfide thin films are deposited using a vapor phase rhenium halide precursor, a reducing agent and a sulfur precursor. The deposited TMDC films can be etched by chemical vapor etching using an oxidant such as O2 as the etching reactant and an inert gas such as N2 to remove excess etching reactant. The TMDC thin films may find use, for example, as 2D materials.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: May 9, 2023
    Assignee: ASM IP Holding B.V.
    Inventors: Jani Hämäläinen, Mikko Ritala, Markku Leskelä
  • Patent number: 11610784
    Abstract: A method for introducing at least one cutout, in particular in the form of an aperture, into a sheetlike workpiece having a thickness of less than 3 mm, involving detecting a laser beam onto the surface of the workpiece, selecting the exposure time of the laser beam to be extremely short so that only a modification of the workpiece concentrically around a beam axis of the laser beam occurs, such a modified region having defects resulting in a chain of blisters, and, as a result of the action of a corrosive medium, anisotropically removing material by successive etching in those regions of the workpiece that are formed by the defects and have previously been modified by the laser beam, resulting, along the cylindrical zone of action, in producing a cutout as an aperture in the workpiece.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: March 21, 2023
    Assignee: LPKF LASER & ELECTRONICS SE
    Inventors: Norbert Ambrosius, Roman Ostholt
  • Patent number: 11603592
    Abstract: A surface treatment agent capable of forming a hexavalent chromium-free chemical conversion coating that can provide an excellent corrosion-resistant coating on various metallic materials; a metallic material having a surface treatment coating obtained therefrom; and a method of producing the same.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 14, 2023
    Assignee: Nihon Parkerizing Co., Ltd.
    Inventors: Yusuke Yamamoto, Satoshi Kawabe
  • Patent number: 11581189
    Abstract: Embodiments described herein relate to methods forming optical device structures. One embodiment of the method includes exposing a substrate to ions at an ion angle relative to a surface normal of a surface of the substrate to form an initial depth of a plurality of depths. A patterned mask is disposed over the substrate and includes two or more projections defining exposed portions of the substrate or a device layer disposed on the substrate. Each projection has a trailing edge at a bottom surface contacting the device layer, a leading edge at a top surface of each projection, and a height from the top surface to the device layer. Exposing the substrate to ions at the ion angle is repeated to form at least one subsequent depth of the plurality of depths.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: February 14, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Ludovic Godet, Rutger Meyer Timmerman Thijssen
  • Patent number: 11572490
    Abstract: A polishing liquid containing abrasive grains, a hydroxy acid, a polyol, and a liquid medium, in which a zeta potential of the abrasive grains is positive, and the hydroxy acid has one carboxyl group and one to three hydroxyl groups.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 7, 2023
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventor: Tomohiro Iwano
  • Patent number: 11567247
    Abstract: A plasma etching method using a Faraday cage, which effectively produces a blazed grating pattern.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: January 31, 2023
    Assignee: LG CHEM, LTD.
    Inventors: Eun Kyu Her, Jeong Ho Park, Seong Min Park, Sang Choll Han, Bu Gon Shin
  • Patent number: 11551935
    Abstract: A substrate processing method includes: holding a substrate having a processing target surface and an opposite surface which is opposite to the processing target surface; preheating a center portion of the opposite surface of the substrate; after the preheating, ejecting a sulfuric acid hydrogen peroxide mixture (SPM) to a peripheral edge portion of the processing target surface of the substrate; and after the ejecting, moving an ejection position of the SPM from the peripheral edge portion of the processing target surface to a center portion of the substrate.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: January 10, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takashi Nakazawa, Kazuyoshi Shinohara
  • Patent number: 11551917
    Abstract: One or more embodiments described herein relate to abatement systems for reducing Br2 and Cl2 in semiconductor processes. In embodiments described herein, semiconductor etch processes are performed within process chambers. Thereafter, fluorinated greenhouse gases (F-GHGs), HBr, and Cl2 gases exit the process chamber and enter a plasma reactor. Reagent gases are delivered from a reagent gas delivery apparatus to the plasma reactor to mix with the process gases. Radio frequency (RF) power is applied to the plasma reactor, which adds energy and “excites” the gases within the process chamber. When HBr is energized, it forms Br2. Br2 and Cl2 are corrosive and toxic. However, the addition of H2O in the plasma reactor quenches the Br2 and Cl2 emissions, as the H atoms recombine with the Br atoms and the Cl atoms to form HBr and HCl. HBr and HCl are readily water-soluble and removed through a wet scrubber.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: January 10, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Joseph A. Van Gompel, James L'Heureux
  • Patent number: 11543376
    Abstract: The present invention relates to a method for manufacturing a sample for thin film property measurement and analysis, and a sample manufactured thereby and, more specifically, to: a method for manufacturing a sample capable of measuring or analyzing various properties in one sample; and a sample manufactured thereby.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: January 3, 2023
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Ki-Bum Kim, Min-Sik Kim, Hyun-Mi Kim, Ki-Ju Kim
  • Patent number: 11529605
    Abstract: Devices for photoelectrodes for water splitting based on indium nanowires on flexible substrates as well as methods of manufacture by transferring nanowire arrays to flexible substrates.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: December 20, 2022
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Rami Tarek El Afandy, Mohamed Ebaid Abdrabou Hussein, Boon S. Ooi, Tien Khee Ng
  • Patent number: 11521857
    Abstract: The present disclosure, in some embodiments, relates to a method of performing an etch process. The method is performed by forming a first plurality of openings defined by first sidewalls of a mask disposed over a substrate. A cut layer is between two of the first plurality of openings. A spacer is formed onto the first sidewalls of the mask and a second plurality of openings are formed. The second plurality of openings are defined by second sidewalls of the mask and are separated by the spacer. The substrate is etched according to the mask and the spacer.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 11521860
    Abstract: A method for selectively etching layers of a first material with respect to layers of a second material in a stack is provided. The layers of the first material are partially etched with respect to the layers of the second material. A deposition layer is selectively deposited on the stack, wherein portions of the deposition layer covering the layers of the second material are thicker than portions covering the layers of the first material, the selective depositing comprising providing a first reactant, purging some of the first reactant, wherein some undeposited first reactant is not purged, and providing a second reactant, wherein the undeposited first reactant combines with the second reactant and selectively deposits on the layers of the second material with respect to the layers of the first material. The layers of the first material are selectively etched with respect to the layers of the second material.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: December 6, 2022
    Assignee: Lam Research Corporation
    Inventors: Jun Xue, Samantha SiamHwa Tan, Mohand Brouri, Yuanhui Li, Daniel Peter, Alexander Kabansky
  • Patent number: 11469095
    Abstract: The present disclosure relates to a method for forming a cavity that traverses a stack of layers including a bottom layer, a first portion of which locally presents an excess thickness, the method comprising a first step of non-selective etching and a second step of selective etching vertically in line with the first portion.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: October 11, 2022
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Delia Ristoiu, Pierre Bar, Francois Leverd
  • Patent number: 11443954
    Abstract: An apparatus and method process a substrate in a first session and a second session. In the first session, a hybrid gas application cycle is performed in a chamber that holds the substrate. A first gas is introduced for a first time period so components of the first gas adsorb onto the substrate. Subsequently, a second gas is introduced for a second time period so the second gas reacts with the components of the first gas to provide a protective layer on sidewalls of a pattern of the substrate, and the second gas etches a bottom portion of the pattern, a ratio of the first time period to the second time period being a use-ratio. Then, in a second session, the hybrid gas application cycle is repeated with a different use-ratio that corresponds with a vertical dimension of the pattern.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 13, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takayuki Katsunuma
  • Patent number: 11417525
    Abstract: Methods of self-aligned multiple patterning. A hardmask is deposited over an interlayer dielectric layer. A mandrel is formed over the hardmask. A block mask is formed that covers a first lengthwise section of the mandrel and that exposes second and third lengthwise sections of the mandrel. After forming the block mask, the second and third lengthwise sections of the mandrel are removed to define a pattern including respective first and second mandrel lines that are separated from each other by the first lengthwise section of the mandrel. The first mandrel line and the second mandrel line expose respective portions of the hardmask, and the first lengthwise section of the mandrel line covers another portion of the hardmask. The pattern is transferred to the hardmask with an etching process, and subsequently transferred to the interlayer dielectric layer with another etching process.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: August 16, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Martin O'Toole, Keith Donegan, Brendan O'Brien, Hsueh-Chung Chen, Terry A. Spooner, Craig Child, Sean Reidy, Ravi Prakash Srivastava, Louis Lanzerotti, Atsushi Ogino
  • Patent number: 11417534
    Abstract: Exemplary methods for removing nitride may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The methods may further include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor and flowing the plasma effluents into a processing region of the semiconductor processing chamber housing a substrate. The substrate may include a high-aspect-ratio feature. The substrate may further include a region of exposed nitride and a region of exposed oxide. The methods may further include providing a hydrogen-containing precursor to the processing region to produce an etchant. At least a portion of the exposed nitride may be removed with the etchant.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: August 16, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Ming Xia, Dongqing Yang, Ching-Mei Hsu
  • Patent number: 11410834
    Abstract: A substrate processing apparatus of the present disclosure includes a processing container capable of being vacuum-exhausted, a lower electrode, and an upper electrode. A target substrate can be placed on the lower electrode. The upper electrode is disposed in the processing container so as to face the lower electrode. A substrate processing method of the present disclosure includes performing a first process on the target substrate using an AC voltage without using a DC pulse voltage, and performing a second process on the target substrate using the DC pulse voltage.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 9, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Keiichi Tanaka, Tatsuo Matsudo
  • Patent number: 11401441
    Abstract: Provided are Chemical Mechanical Planarization (CMP) formulations that offer high and tunable Cu removal rates and low copper dishing for the broad or advanced node copper or Through Silica Via (TSV). The CMP compositions provide high selectivity of Cu film vs. other barrier layers, such as Ta, TaN, Ti, and TiN, and dielectric films, such as TEOS, low-k, and ultra low-k films. The CMP polishing formulations comprise solvent, abrasive, at least three chelators selected from the group consisting of amino acids, amino acid derivatives, organic amine, and combinations therefor; wherein at least one chelator is an amino acid or an amino acid derivative. Additionally, organic quaternary ammonium salt, corrosion inhibitor, oxidizer, pH adjustor and biocide are used in the formulations.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 2, 2022
    Assignee: VERSUM MATERIALS US, LLC
    Inventors: Xiaobo Shi, Laura M. Matz, Chris Keh-Yeuan Li, Ming-Shih Tsai, Pao-Chia Pan, Chad Chang-Tse Hsieh, Rung-Je Yang, Blake J. Lew, Mark Leonard O'Neill, Agnes Derecskei
  • Patent number: 11387115
    Abstract: Apparatus, systems, and methods for conducting a silicon containing material removal process on a workpiece are provided. In one example implementation, the method can include generating species from a process gas in a first chamber using an inductive coupling element. The method can include introducing a fluorine containing gas with the species to create a mixture. The mixture can include exposing a silicon structure of the workpiece to the mixture to remove at least a portion of the silicon structure.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: July 12, 2022
    Assignees: BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY, CO., LTD, MATTSON TECHNOLOGY, INC.
    Inventors: Chun Yan, Tsai Wen Sung, Sio On Lo, Hua Chung, Michael X. Yang