Patents Examined by Thomas T Pham
  • Patent number: 10745588
    Abstract: This invention provides a silicon wafer polishing composition used in the presence of an abrasive. The composition comprises a silicon wafer polishing accelerator, an amide group-containing polymer, and water. The amide group-containing polymer has a building unit A in its main chain. The building unit A comprises a main chain carbon atom constituting the main chain of the amide group-containing polymer and a secondary amide group or a tertiary amide group. The carbonyl carbon atom constituting the secondary amide group or tertiary amide group is directly coupled to the main chain carbon atom.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: August 18, 2020
    Assignees: FUJIMI INCORPORATED, TOAGOSEI CO., LTD.
    Inventors: Kohsuke Tsuchiya, Hisanori Tansho, Taiki Ichitsubo, Yoshio Mori
  • Patent number: 10727075
    Abstract: Embodiments of the present disclosure generally provide a method and apparatus for forming features in a material layer utilizing EUV technologies. In one embodiment, a method of patterning a substrate includes disposing a patterned photoresist layer on a mask layer disposed on a substrate, wherein the patterned photoresist layer has openings with different widths defined in the patterned photoresist layer, forming a compensatory layer along sidewalls of the patterned photoresist layer to modify the widths of the openings and etching the mask layer through the openings with the modified width.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: July 28, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sang Wook Kim, Zhibin Wang, Kyoungjin Lee, Byungkook Kong
  • Patent number: 10729018
    Abstract: To stably produce a laminate wherein heat resistant resin layers are laminated on both surfaces of a fluorinated resin layer, by thermal lamination.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 28, 2020
    Assignee: AGC Inc.
    Inventors: Toru Sasaki, Wataru Kasai
  • Patent number: 10720322
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing the sidewall portion of the film by wet etching which removes the sidewall portion of the film more predominantly than the top/bottom portion according to the different chemical resistance properties.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 21, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
  • Patent number: 10685871
    Abstract: The present invention provides a method for fabricating a semiconductor structure. A multilayer structure on is formed a substrate, the multilayer structure includes at least a first dielectric layer, a second dielectric layer and an amorphous silicon layer, next, a first etching step is performed, to forma first recess in the amorphous silicon layer and in the second dielectric layer, parts of the first dielectric layer is exposed by the first recess, afterwards, a hard mask layer is formed in the first recess, a second etching step is then performed to remove the hard mask layer and to expose a surface of the first dielectric layer, and a third etching step is performed with the remaining hard mask layer, to remove a portion of the first dielectric layer, so as to form a second recess in the first dielectric layer.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 16, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 10672619
    Abstract: Provided is a material composition and method that includes forming a patterned resist layer on a substrate, where the patterned resist layer has a first line width roughness. In various embodiments, the patterned resist layer is coated with a treatment material, where a first portion of the treatment material bonds to surfaces of the patterned resist layer. In some embodiments, a second portion of the treatment material (e.g., not bonded to surfaces of the patterned resist layer) is removed, thereby providing a treated patterned resist layer, where the treated patterned resist layer has a second line width roughness less than the first line width roughness.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Siao-Shan Wang, Cheng-Han Wu, Ching-Yu Chang, Chin-Hsiang Lin
  • Patent number: 10662272
    Abstract: Embodiments provide a polishing composition for a magnetic disk substrate containing colloidal silica, a water-soluble polymer, and water. The water-soluble polymer compound is a copolymer containing a monomer having a carboxylic acid group, a monomer having an amide group, and a monomer having a sulfonic acid group as essential monomers. The water-soluble polymer compound has a weight average molecular weight of 1,000 to 1,000,000.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: May 26, 2020
    Assignee: YAMAGUCHI SEIKEN KOGYO CO., LTD.
    Inventor: Akira Sugawa
  • Patent number: 10662532
    Abstract: A method of manufacturing an embossing element for decorative surfaces includes the steps of: a) UV curable inkjet printing a decorative pattern on a metallic surface; and b) forming a relief by etching metal from the metallic surface.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: May 26, 2020
    Assignees: AGFA-GEVAERT N.V., AGFA NV
    Inventors: Roel De Mondt, Rita Torfs, Johan Loccufier
  • Patent number: 10658161
    Abstract: In-situ low pressure chamber cleans and gas nozzle apparatus for plasma processing systems employing in-situ deposited chamber coatings. Certain chamber clean embodiments for conductor etch applications include an NF3-based plasma clean performed at pressures below 30 mT to remove in-situ deposited SiOx coatings from interior surfaces of a gas nozzle hole. Embodiments include a gas nozzle with bottom holes dimensioned sufficiently small to reduce or prevent the in-situ deposited chamber coatings from building up a SiOx deposits on interior surfaces of a nozzle hole.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 19, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Andrew Nguyen, Changhun Lee, Xiaoming He, Meihua Shen
  • Patent number: 10658196
    Abstract: A chemical-mechanical polishing slurry composition, comprising a polishing agent, an amine-based polishing activator, and a roughness adjusting agent, wherein the amine-based polishing activator is a tertiary or quaternary amine, and the roughness adjusting agent is a disaccharide. According to the slurry composition, the roughness of tungsten and silicon oxide films can be modified and the number of particles present on the wafer surface after polishing can be reduces so that defects of the wafer can be prevented.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 19, 2020
    Inventors: Hyeong Ju Lee, Seok Joo Kim, Kyung Il Park
  • Patent number: 10644239
    Abstract: The method for producing an OLED micro-display on a silicon wafer uses a collimating shadow mask formed on a silicon substrate. The mask is fabricated by depositing a material layer on the front side and on the back side of the substrate and etching a portion of the layer on the back side of the substrate to a reduced thickness of at least 20 microns. At least one opening is created in the etched portion of the substrate. The substrate beneath the opening is removed to create the mask. The mask is situated at a location spaced from the surface of the silicon wafer and exposed to a linear evaporation source. Organic layers are then deposited on the silicon wafer in a location aligned with the mask opening.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 5, 2020
    Assignee: eMagin Corporation
    Inventors: Amalkumar Ghosh, Fridrich Vazan
  • Patent number: 10626498
    Abstract: There is provided a method of processing a target object to be processed including a porous film and a mask. The method include supplying a first gas into a processing chamber of a plasma processing apparatus in which the target object including the porous film is accommodated, and generating a plasma of a second gas in the processing chamber to remove the mask. The first gas is a processing gas having a saturated vapor pressure of less than or equal to 133.3 Pa at a temperature of a stage on which the target object is mounted in the processing chamber, or includes the processing gas. In the step of supplying the first gas, no plasma is generated, and a partial pressure of the processing gas supplied into the processing chamber is greater than or equal to 20% of the saturated vapor pressure.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: April 21, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Tahara, Eiichi Nishimura
  • Patent number: 10629427
    Abstract: Methods for processing a substrate, such as bevel etch processing, are provided. In one embodiment, a method includes placing a substrate on a cover plate inside of a processing chamber, where the substrate has a center and a bevel edge and contains a dielectric layer thereon, the processing chamber contains a mask disposed above the substrate and an edge ring disposed under the substrate, the edge ring has an annular body, and the cover plate is disposed on a support assembly. The method further includes heating the substrate with a heater attached to the support assembly, raising the edge ring to contact the mask, flowing a process gas containing an etchant along an outer surface of the mask and to the bevel edge, where the process gas is ignited to produce a plasma, and exposing an upper surface of the substrate at the bevel edge to the process gas.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: April 21, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zonghui Su, Vinay Prabhakar, Abdul Aziz Khaja, Jeongmin Lee
  • Patent number: 10595967
    Abstract: A process for providing a topography to the surface of a dental implant, the surface being made of a ceramic material having yttria-stabilized zirconia, the process including: providing a macroscopic roughness to the surface of the dental implant by a mechanical process and/or injection molding technique; and etching at least a part of the roughened surface, wherein etching is carried out using an etching solution having hydrofluoric acid at a temperature of 70° C. at least, such that discrete grains or agglomerates of grains are removed from the yttria-stabilized zirconia, thereby forming recesses and cavities in the roughened surface is disclosed.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: March 24, 2020
    Assignee: STRAUMANN HOLDING AG
    Inventors: Frank Homann, Philippe Habersetzer
  • Patent number: 10591817
    Abstract: The present invention provides a method for producing a composition for forming a coating film for a lithography used in manufacture of a semiconductor device by using a producing apparatus provided with a metal adsorbent and a filter, comprising the steps of: (1) introducing a solvent used in the composition into the producing apparatus, (2) circulating the solvent in the producing apparatus to adsorb a metal impurity by the metal adsorbent, (3) adding a raw material of the composition into the circulated solvent and homogenizing them to prepare the composition, and (4) circulating the prepared composition in the producing apparatus to remove a microscopic foreign matter by the filter. This method enables to produce a composition for forming a coating film for a lithography with its metal impurities, which cause an etching defect, extremely reduced.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: March 17, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Tsutomu Ogihara, Motoaki Iwabuchi
  • Patent number: 10593559
    Abstract: An etching process in a capacitor process for DRAM is described. A substrate is provided, which has thereon a silicon layer and metal electrodes in the silicon layer. The silicon layer is removed using a liquid etchant composition. The liquid etchant composition contains tetramethylammonium hydroxide (TMAH), an additive including hydroxylamine or a metal corrosion inhibitor, and water as a solvent.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: March 17, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Michael Tristan Andreas
  • Patent number: 10584073
    Abstract: Contemplated compositions and methods for treating in service concrete includes the step of contacting a portion of the in service concrete with an composition, wherein the composition comprises a base and at least one of an acid and a salt of an acid in an amount effective to convert insoluble calcium salts into soluble calcium gluconates that can be washed away with water or other liquid.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: March 10, 2020
    Assignee: Protocol Environmental Solutions Inc.
    Inventor: Sergio Vitomir
  • Patent number: 10586714
    Abstract: A thin film transistor substrate includes a gate electrode arranged on a substrate, a gate insulation layer arranged on the gate electrode, an active pattern arranged on the gate insulation layer, a source electrode overlapping a first end portion of the active pattern, and a drain electrode overlapping a second and opposite end portion of the active pattern. A fluorocarbon-like material is arranged on one or more of surfaces of at least one of the active pattern, the source electrode and the drain electrode, and on a photoresist pattern used in the formation process of the thin film substrate. The fluorocarbon-like material on the photoresist pattern serves to maintain a shape and size of the photoresist pattern during subsequent patterning processes.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 10, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun-Min Cho, Dong-Il Kim
  • Patent number: 10577445
    Abstract: Embodiments relate to a polishing composition is an aqueous composition containing at least colloidal silica, wet-process silica particles, and a water-soluble polymer compound. The water-soluble polymer compound is a copolymer containing a monomer having a carboxylic acid group, a monomer having an amide group, and a monomer having a sulfonic acid group as essential monomers.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 3, 2020
    Assignee: YAMAGUCHI SEIKEN KOGYO CO., LTD.
    Inventor: Toru Iwata
  • Patent number: 10563300
    Abstract: A method is employed to separate a carbon structure, which is disposed on a seed structure, from the seed structure. In the method, a carbon structure is deposited on the seed structure in a process chamber of a CVD reactor. The substrate comprising the seed structure (2) and the carbon structure (1) is heated to a process temperature. At least one etching gas is injected into the process chamber, the etching gas having the chemical formula AOmXn, AOmXnYp or AmXn, wherein A is selected from a group of elements that includes S, C and N, wherein O is oxygen, wherein X and Y are different halogens, and wherein m, n and p are natural numbers greater than zero. Through a chemical reaction with the etching gas, the seed structure is converted into a gaseous reaction product. A carrier gas flow is used to remove the gaseous reaction product from the process chamber.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: February 18, 2020
    Assignee: AIXTRON SE
    Inventors: Kenneth B. K. Teo, Alexandre Jouvray, Jai Matharu, Simon Thomas