Patents Examined by Thomas T Pham
  • Patent number: 10563319
    Abstract: A process for making at least one porous area (ZP) of a microelectronic structure in at least one part of an conducting active layer (6), the active layer (6) forming a front face of a stack, the stack comprising a back face (2) of conducting material and an insulating layer (4) interposed between the active layer (6) and the back face (2), said process comprising the steps of: a) making at least one contact pad (14) between the back face (2) and the active layer (6) through the insulation layer (2), b) placing the stack into an electrochemical bath, c) applying an electrical current between the back face (2) and the active layer (6) through the contact pad (14) causing porosification of an area (ZP) of the active layer (6) in the vicinity of the contact pad (14), d) forming the microelectronic structure.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: February 18, 2020
    Assignee: COMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Eric Ollier, Frederic-Xavier Gaillard, Carine Marcoux
  • Patent number: 10538090
    Abstract: A method for manufacturing a perforated substrate includes forming a through-hole extending through a substrate from a first surface to a second surface opposite the first surface; forming a film on the first surface, a sidewall of the through-hole, and the second surface; forming a resist on the first surface; patterning the resist such that the resist closes an opening of the through-hole in the first surface; etching the film on the first surface using the resist as a mask; before the etching step, forming an inspection member on the second surface such that the inspection member closes an opening of the through-hole in the second surface; and determining whether there is a film patterning defect or a flaw that causes a film patterning defect.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 21, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Seiichiro Yaginuma, Masataka Nagai, Masaya Uyama
  • Patent number: 10541184
    Abstract: Embodiments may include a method of etching. The method may also include flowing a gas mixture through a plasma discharge to form plasma effluents. The method may further include flowing the plasma effluents through a plurality of apertures to a layer on a substrate. The layer may have a first thickness. In addition, the method may include etching the layer with the plasma effluents. The method may also include measuring the intensity of emission from a reaction of plasma effluents with the layer. The method may further include summing the intensity of the emission while the plasma effluents are being flowed to the layer to obtain an integrated intensity. The method may then include comparing the integrated intensity to a reference value corresponding to a target etch thickness. The method may include extinguishing the plasma discharge when the integrated intensity is equal to or greater than the reference value.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: January 21, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Soonwook Jung, Soonam Park, Dmitry Lubomirsky
  • Patent number: 10541147
    Abstract: A method for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride, includes: preparing a target object including the first region and the second region in a processing chamber of a plasma processing apparatus; and generating a plasma of a processing gas containing a fluorocarbon gas and a rare gas in the processing chamber. In the generating the plasma of the processing gas, a self-bias potential of a lower electrode on which the target object is mounted is greater than or equal to 4V and smaller than or equal to 350V and a flow rate of the rare gas in the processing gas is 250 to 5000 times of a flow rate of the fluorocarbon gas in the processing gas.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 21, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Tabata, Takayuki Katsunuma, Masanobu Honda
  • Patent number: 10527791
    Abstract: A semiconductor device includes a substrate, a trench in the substrate, the trench having an inclined sidewall, a reflective layer over the inclined sidewall, a grating structure over the substrate, and a waveguide in the trench. The waveguide is configured to guide optical signals between the grating structure and the reflective layer.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Hao Kuo, Tien-Yu Huang
  • Patent number: 10529554
    Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: January 7, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Dai Ishikawa, Atsuki Fukazawa, Eiichiro Shiba, Shinya Ueda, Taishi Ebisudani, SeungJu Chun, YongMin Yoo, YoonKi Min, SeYong Kim, JongWan Choi
  • Patent number: 10465294
    Abstract: Methods are described herein for etching metal films which are difficult to volatize. The methods include exposing a metal film to a chlorine-containing precursor (e.g. Cl2). Chlorine is then removed from the substrate processing region. A carbon-and-nitrogen-containing precursor (e.g. TMEDA) is delivered to the substrate processing region to form volatile metal complexes which desorb from the surface of the metal film. The methods presented remove metal while very slowly removing the other exposed materials. A thin metal oxide layer may be present on the surface of the metal layer, in which case a local plasma from hydrogen may be used to remove the oxygen or amorphize the near surface region, which has been found to increase the overall etch rate.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: November 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Xikun Wang, Jie Liu, Anchuan Wang, Nitin K. Ingle, Jeffrey W. Anthis, Benjamin Schmiege
  • Patent number: 10468268
    Abstract: There is provided an etching method for etching an object to be processed by using a substrate processing apparatus including a process chamber including a first electrode and a second electrode disposed opposite to the first electrode to receive the object to be processed thereon. The etching method includes a process of removing at least one of a first polymer and a second polymer by etching the object to be processed on which a pattern of the first polymer and the second polymer is formed by phase separation of a block copolymer containing the first polymer and the second polymer at a temperature lower than or equal to 10 degrees C. by using plasma of a process gas.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: November 5, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Ryoichi Yoshida
  • Patent number: 10410839
    Abstract: In an example embodiment a method of processing a substrate includes forming a plasma in a plasma chamber and using charged grids to form an ion beam and to thereby accelerate ions from the plasma chamber to a processing chamber. An auxiliary heater, which may be a radiant heater, may be used to pre-heat a grid to a saturation state to accelerate heating and concomitant distortion of the grid. A process recipe may pre-compensate for distortion of the grid.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: September 10, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yil-Hyung Lee, Yoo-Chul Kong, Jong-Kyu Kim, Seok-Woo Nam, Jong-Soon Park, Kyoung-Sub Shin
  • Patent number: 10366890
    Abstract: Techniques herein enable integrating stack materials and multiple color materials that require no corrosive gases for etching. Techniques enable a multi-line layer for self-aligned pattern shrinking in which all layers or colors or materials can be limited to silicon-containing materials and organic materials. Such techniques enable self-aligned block integration for 5 nm back-end-of-line trench patterning with an all non-corrosive etch compatible stack for self-aligned block. Embodiments include using lines of a same material but at different heights to provided etch selectivity to one of several lines based on type of material and/or height of material and etch rate.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: July 30, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Anton J. deVilliers, Nihar Mohanty
  • Patent number: 10361080
    Abstract: A patterning method is disclosed. A hard mask layer, a lower pattern transfer layer, an upper pattern transfer layer are formed on a target layer. A first SARP process is performed to pattern the upper pattern transfer layer into an upper pattern mask. A second SARP process is performed to pattern the lower pattern transfer layer into a lower pattern mask. The upper pattern mask and the lower pattern mask define hole patterns. The hole patterns is filled with a dielectric layer. The dielectric layer and the upper pattern mask are etched back until the lower pattern mask is exposed. The lower pattern mask is removed, thereby forming island patterns. Using the island patterns as an etching hard mask, the hard mask layer is patterned into hard mask patterns. Using the hard mask patterns as an etching hard mask, the target layer is patterned into target patterns.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: July 23, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10354889
    Abstract: Processing methods may be performed to limit damage of features of a substrate, such as missing fin damage. The methods may include forming a plasma of an inert precursor within a processing region of a processing chamber. Effluents of the plasma of the inert precursor may be utilized to passivate an exposed region of an oxygen-containing material that extends about a feature formed on a semiconductor substrate. A plasma of a hydrogen-containing precursor may also be formed within the processing region. Effluents of the plasma of the hydrogen-containing precursor may be directed, with DC bias, towards an exposed silicon-containing material on the semiconductor substrate. The methods may also include anisotropically etching the exposed silicon-containing material with the plasma effluents of the hydrogen-containing precursor, where the plasma effluents of the hydrogen-containing precursor selectively etch silicon relative to silicon oxide.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: July 16, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Tom Choi, Mandar B. Pandit, Mang-Mang Ling, Nitin K. Ingle
  • Patent number: 10345520
    Abstract: An optical device and a method of manufacturing an optical device, including a ridge waveguide second, and a strip-loaded ridge waveguide section, comprises applying two different protective layers and two separate etches at two different depths. The protective layers overlap to protect the same section of the optical device, and to limit the surfaces of optical device to exposure to multiple etches, except at edges where the protective layers overlap.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: July 9, 2019
    Assignee: Elenion Technologies, LLC
    Inventors: Thomas Wetteland Baehr-Jones, Ruizhi Shi
  • Patent number: 10312114
    Abstract: This substrate processing method includes supplying a chemical liquid to an upper surface of a substrate and rinsing away the chemical liquid adhering to the upper surface of the substrate by holding a puddled rinse liquid on the substrate while maintaining a rotation speed of the substrate at a zero or low speed, and a chemical liquid puddle step of holding a liquid film of a puddled chemical liquid on the upper surface of the substrate while maintaining the rotation speed of the substrate at a zero or low speed, and the rinsing step is performed subsequent to finishing the chemical liquid puddle step, and the rinsing step includes supplying a rinse liquid to the upper surface of the substrate and then replacing the liquid film of the chemical liquid held on the upper surface of the substrate with the rinse liquid.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: June 4, 2019
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Asuka Yoshizumi, Ayumi Higuchi
  • Patent number: 10276364
    Abstract: Implementations described herein generally relate to methods and apparatus for processing a substrate. More particularly, implementations described herein relate to methods and an apparatus for bevel etch processing. In one embodiment, a method of cleaning a bevel edge of a semiconductor substrate is provided. The method includes placing a substrate on a cover plate inside of a processing chamber, the substrate having a deposition layer, which includes a center, and a bevel edge. A mask is placed over the substrate. The edge ring is disposed around/under the substrate. The method also includes flowing a process gas mixture adjacent the bevel edge, and flowing a purge gas through a first hole, a second hole, and a third hole of the mask in the center of the substrate adjacent a top of the substrate.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: April 30, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Zonghui Su, Vinay Prabhakar, Abdul Aziz Khaja, Jeongmin Lee
  • Patent number: 10272657
    Abstract: A method of micropatterning a substrate is provided. The method comprises providing a template substrate having a patterned surface inked with a composition of interest; contacting the patterned surface with an intermediate substrate, thereby transferring the composition to the surface of the intermediate substrate; contacting the surface of the intermediate substrate comprising the composition with the substrate; and removing the intermediate substrate by dissolution using a solvent. A patterned substrate formed using the method, as well as a biosensor comprising the patterned substrate is also provided.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: April 30, 2019
    Assignee: Nanyang Technological University
    Inventors: Haiyang Yu, Lay Poh Tan
  • Patent number: 10274819
    Abstract: A method for fabricating a pellicle for EUV lithography processes includes placing a hard mask in contact with a surface of a substrate. In some embodiments, the hard mask is configured to pattern the surface of the substrate to include a first region and a second region surrounding the first region. By way of example, while the mask in positioned in contact with the substrate, an etch process of the substrate is performed to etch the first and second regions into the substrate. Thereafter, an excess substrate region is removed so as to separate the etched first region from the excess substrate region. In various embodiments, the etched and separated first region serves as a pellicle for an extreme ultraviolet (EUV) lithography process.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Cheng Hsu, Chih-Tsung Shih, Jeng-Horng Chen, Chih-Cheng Lin, Hsin-Chang Lee, Shinn-Sheng Yu, Ta-Cheng Lien, Anthony Yen
  • Patent number: 10260153
    Abstract: The invention relates to compositions and methods that are useful in etching a metal surface. In particular, the invention relates to novel acid compositions and methods of using such compositions in etching a metal surface, preferably an aluminum surface prior to anodizing to dissolve impurities, imperfections, scale, and oxide. The compositions are effective in maintaining their etching capacity and in removing smut produced by the etching of a surface as well as in general cleaning.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: April 16, 2019
    Assignee: Houghton Technical Corp.
    Inventor: Mores Basaly
  • Patent number: 10240050
    Abstract: A method of producing an article is described. The method includes (a) providing a substrate comprising an etchable surface layer; (b) coating the etchable surface layer with a composition comprising a non-volatile, etch-resistant component in a volatile liquid carrier; and (c) drying the composition to remove the liquid carrier, whereupon the non-volatile, etch-resistant component self-assembles to form etch-resistant traces on the etchable surface layer. The liquid carrier is in the form of an emulsion comprising a continuous phase and a second phase in the form of domains dispersed in the continuous phase.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: March 26, 2019
    Assignee: Clearview Films Ltd.
    Inventors: Arkady Garbar, Eric L. Granstrom, Joseph Masrud
  • Patent number: 10236182
    Abstract: A method of forming a nitrogen-doped amorphous carbon layer on a substrate in a processing chamber is provided. The method generally includes depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a nitrogen-doped amorphous carbon layer on the patterned features and the exposed upper surface of the substrate, selectively removing the nitrogen-doped amorphous carbon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the nitrogen-doped amorphous carbon layer, and removing the patterned features from the substrate.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: March 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sungjin Kim, Deenesh Padhi, Sung Hyun Hong, Bok Hoen Kim, Derek R. Witty