Patents Examined by Thuan Do
  • Patent number: 9842177
    Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing at least one program, and a method for behavioral modeling of jitters due to power supply noise for input/output (I/O) buffers. The method may include accessing physical model data describing a physical structure of an integrated circuit device, and accessing a behavioral model schema for evaluating electrical characteristics of the integrated circuit device including jitter effects introduced by power noise in the integrated circuit device. The method may further include generating behavioral model data based on the physical model data, the behavioral model data including the electrical characteristics of integrated circuit device. The method may further include providing a data file including the behavioral model data.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: December 12, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yingxin Sun, Yun Dai
  • Patent number: 9834100
    Abstract: A charge/discharge system includes: first and second electric chargers that supplies electric power to a motor generator and charges electric power generated by a motor generator; an electric power converter; and a controller. The controller controls the electric power converter such that electric power charged in the first electric charger is supplied to the motor generator, electric power charged in the second electric charger is charged in the first electric charger when a charging capacity of the first electric charger is lower than a second predetermined value. The driving force of the motor generator is reduced depending on the charging capacity when the charging capacity of the first electric charger is lower than the first predetermined value.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: December 5, 2017
    Assignee: Volvo Truck Corporation
    Inventors: Kunihiko Hikiri, Noriaki Miyake
  • Patent number: 9811615
    Abstract: Various aspects of the disclosed technology relate to techniques of retargeting layout features. A process window simulation on a layout design is performed to generate process window information that comprises predicted print positions of layout features computed under various process conditions. Retargeted print positions for a plurality of edge fragments in the layout design are then determined based on minimizing a combined change of targeted print positions for the plurality of edge fragments under constraints represented based on the process window information and specification limits for printed layout features. Based on the retargeted print positions, positions of the plurality of edge fragments are adjusted for optical proximity correction.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: November 7, 2017
    Assignee: Mentor Graphics Corporation
    Inventors: George P. Lippincott, Zhitang Yu, Xima Zhang
  • Patent number: 9811621
    Abstract: Circuit design computing equipment may perform depopulation operations, constraint generation, and repopulation operations in a circuit design in anticipation of register retiming operations. A depopulation operation before placement and/or before routing operations may prevent the respective placement and/or routing operations from placing and/or routing registers from the circuit design. Constraint generation may create constraints for placement and/or routing operations that allow for the reinsertion of registers after routing operations. Repopulation operations may reinsert registers in the circuit design after routing operations according to the constraints. If desired, the circuit design computing equipment may perform register retiming operations to further improve the performance of the circuit design.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 7, 2017
    Assignee: Altera Corporation
    Inventors: Kimberly Anne Bozman, David Ian Milton, Nishanth Sinnadurai
  • Patent number: 9812888
    Abstract: The invention disclosed is a method for decreasing the internal resistance or impedance of a battery or electrochemical cell is described which comprises the step of discharging the battery or cell until it reaches an overdischarge condition and maintaining the battery or cell in the overdischarge condition for a period of time sufficient to effect a diminution of the internal resistance or impedance of a battery or electrochemical cell; and a battery or electrochemical cell having a reduced impedance.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: November 7, 2017
    Assignee: Bathium Canada Inc.
    Inventors: Patrick Leblanc, Frederic Cotton, Thierry Guena, Cedric Reboul-Salze, Marc Deschamps, Thomas Calvez, Vincent Bodenez, Philippe Bernardo, Mathieu Dru
  • Patent number: 9785733
    Abstract: A fillet at the connection between a round land and a connecting line by calculating a first point of contact (POC) between the connecting line and a first circle and a second POC between the round land and the first circle, the first circle being in contact with the round land and the connecting line; calculating a third POC between the round land and a second circle and a fourth POC between the connecting line and the second circle, the second circle being in contact with the round land and the connecting line at the opposite side of the first circle; and calculating the arc fillet defined as a region surrounded by a first arc between the first and second POCs, a second arc between the third and fourth POCs, a third arc between the fourth and first POCs, and a line segment between the second and third POCs.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: October 10, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Yoshitaka Nishio, Kazunori Kumagai
  • Patent number: 9785734
    Abstract: A method includes obtaining first data representing a first circuit symbol and second data representing a second circuit symbol. The first circuit symbol has a plurality of first pins having a first position vector associated therewith. The second circuit symbol has a plurality of second pins having a second position vector associated therewith, and each of the plurality of second pins corresponds to a respective one of the plurality of first pins. An adjustment transformation mapping position vectors to transform the position vectors is determined. The adjustment transformation minimizes an error measure that is based on one or more deviations. Each deviation is a deviation between a transformed position vector and the first position vector associated with one of the first pins. The transformed position vector is obtained by applying the adjustment transformation to the second position vector associated with the second pin corresponding to the first pin.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: October 10, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Guntram Jummel
  • Patent number: 9780578
    Abstract: Disclosed is a battery management system for transmitting a secondary protection signal and a diagnosis signal using a small number of insulation elements. N battery management units included in the battery management system transmit at least two pieces of data via one communication line through time division. N data signals transmitted from the N battery management units are transmitted in a sequential order or are mixed to one signal and transmitted to an external device.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: October 3, 2017
    Assignee: LG CHEM, LTD.
    Inventors: Ju-Hyun Kang, Yasuhito Eguchi, Shoji Tanina
  • Patent number: 9780583
    Abstract: A method for recharging a battery pack includes attaching a portable charger to a user, which portable charger includes or is attached to a self-contained power supply and wherein a first charging port of the portable charger is disposed, e.g., on a belt worn by the user, hanging the battery pack on the belt while the battery pack is physically engaged and in electrical communication with a power tool, and initiating a transfer of power from the charger to the battery pack when the first charging port is at least proximal to a second charging port that is in electrical communication with at least one battery cell of the battery pack. A portable charging system capable of performing this method, as well as an adapter for use in performing this method, are also disclosed.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: October 3, 2017
    Assignee: MAKITA CORPORATION
    Inventors: Nobuyasu Furui, Hitoshi Suzuki, Masaaki Fukumoto, Takuya Umemura, Kosuke Ito, Hitoshi Sengiku, Shuji Yoshikawa, Tatsuya Nagahama
  • Patent number: 9773086
    Abstract: Disclosed are techniques for implementing coplanar waveguide transmission lines in an electronic design. These techniques identify one or more electrically conductive shapes and a plurality of edge segments thereof in an electronic design. A plurality of model trace segments may be constructed based in part or in whole upon a plurality of edge segments. One or more coupled line groups may be generated with the plurality of model trace segments and one or more actual trace segments for a model of the electronic design. Electrical analyses or simulations may be performed on the model to generate electrical analysis results. The electronic design may then be devised or revised based on extracted parameter values of the electrical analysis results.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: September 26, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jian Liu, Yanrui Wu
  • Patent number: 9761712
    Abstract: A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors. Sets of adjacent active area regions having a same electrical potential are determined. The sets of adjacent active area regions to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions are merged to form larger active area regions according to a priority.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Albert M. Chu, Terence B. Hook, Seong-Dong Kim
  • Patent number: 9760672
    Abstract: A critical-path timing sensor detects set-up timing failures from a functional critical path to a path flip-flop. The functional critical path carries test data during test mode, and normal data during normal device operation. The path flip-flop's D input and Q output are compared by an exclusive-OR (XOR) gate and sampled by an early capture flip-flop that is clocked by a delayed clock, sampling D and Q just after the path flip-flop is clocked. When set-up time fails, D and Q differ just after the clock edge and a timing failure is latched. Timing failures activate a controller to increase VDD, while VDD is reduced in the absence of timing failures. Process variations are accounted for, allowing for lower power or faster operation. A margin delay between the functional critical path end and the early capture flip-flop detects timing failures before they occur in the path flip-flop.
    Type: Grant
    Filed: July 4, 2015
    Date of Patent: September 12, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sanjiv Taneja, Bradley Quinton, Trent McClements, Andrew Hughes, Sheida Alan, Bozena Kaminska
  • Patent number: 9760670
    Abstract: Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Wang, Wei-Cheng Wu, Kuo-Ching Hsu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 9753363
    Abstract: A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether ?1<?1, wherein ?1 represents model vs. exposure difference and ?1 represents predetermined criteria. The technique further includes completing the model when ?1<?1.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: September 5, 2017
    Assignees: NIKON CORPORATION, NIKON PRECISION INC
    Inventors: Jacek Tyminski, Raluca Popescu, Tomoyuki Matsuyama
  • Patent number: 9744869
    Abstract: Disclosed is an electric power supply system, vehicle and method of operating a vehicle, wherein an electrical power supply system, in particular a traction system, of a vehicle, includes an energy storage module, an inverter, an electric machine, a receiving device adapted to receive an alternating electromagnetic field and to produce an alternating electric current by electromagnetic induction, and a passive electric circuit arrangement adapted to connect the inverter, the electric machine, and the receiving device, wherein the passive electric circuit arrangement includes a first transmission circuit for transferring electric energy between the receiving device and the electric machine, a second transmission circuit for transferring electric energy between the receiving device and the inverter, and a third transmission circuit for transferring electric energy between the inverter and the electric machine, wherein the passive electric circuit arrangement is designed such that at a given charging frequency,
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: August 29, 2017
    Assignee: Bombardier Transportation GmbH
    Inventors: Robert Czainski, Michael Mollers
  • Patent number: 9748778
    Abstract: A power supply apparatus includes: a connection unit to which a battery pack is connected; a power conversion unit which converts direct current power output from the battery pack via the connection unit into a first power; a power plug which is connected to an external power source; a power supplying unit to which a power receiving unit of the external apparatus is connected to supply the first power output from the power conversion unit or a second power which is the power supplied from the external power source via the power plug; and a switching unit which switches between outputting the first power to the power supplying unit and outputting the second power to the power supplying unit.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: August 29, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Shoichi Toya
  • Patent number: 9748839
    Abstract: A digital voltage regulator controller includes control logic, an interface and configuration logic. The control logic is operable to control power stages of a voltage regulator so that groups of one or more of the power stages individually regulate one or more output voltages of the voltage regulator. An external electrical parameter that indicates a location of the controller on a board or a version of the board is measured via the interface. The configuration logic is operable to determine a set of configuration parameters for the voltage regulator based on the location of the controller on the board or the version of the board as indicated by the external electrical parameter, and configure the control logic in accordance with the set of configuration parameters so that each output voltage is regulated based on the location of the controller on the board or the version of the board.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: August 29, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Benjamim Tang
  • Patent number: 9735781
    Abstract: An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: August 15, 2017
    Assignee: SYPHERMEDIA INTERNATIONAL, INC.
    Inventors: Ronald P. Cocchi, Lap Wai Chow, James P. Baukus, Bryan J. Wang
  • Patent number: 9734263
    Abstract: Described is a method and apparatus for efficient pre-silicon validation of an integrated circuit. The method comprises: analyzing an architectural verification environment associated with a hardware description language (HDL) architecture of an integrated circuit, recognizing method calls associated with the architectural verification environment, and generating a list of recognized method calls that is loaded for a debug program to debug the HDL architecture of the integrated circuit.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 15, 2017
    Assignee: Intel Corporation
    Inventors: Erez Kohavi, Evgeniy Ainbinder
  • Patent number: 9727674
    Abstract: A simulator includes a memory for storing a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; and a processor configured to compensate for delay to synchronize digital and analog signals. The processor includes a delay calculator module for generating one of a rising time and a falling time and a standard delay format (SDF) file using the first netlist, the timing library, and the SPEF file; an SDF file converter module for adjusting an interconnect delay description included in the SDF file to compensate for delay using the one of the rising time and the falling time; and a digital simulator module for generating an event using a first driving cell according to a compensated interconnect delay description.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Eun Koo, Young Jin Gu, In Youl Lee