Patents Examined by Thuan Do
  • Patent number: 9652572
    Abstract: A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: May 16, 2017
    Assignee: NXP USA, Inc.
    Inventors: Michael Priel, Eliya Babitsky, Asher Berkovitz, Vladimir Nusimovich
  • Patent number: 9652579
    Abstract: Disclosed are techniques for implementing parallel fills for electronic designs These techniques identify a shape and one or more neighboring shapes of the shape by searching design data of a region of a layout of an electronic design, classify the shape and the one or more neighboring shapes by examining respective characteristics of and to categorize the shape and the one or more neighboring shapes into one or more classes, implement one or more parallel fill shapes for at least one shape of the shape and the one or more neighboring shapes by aggregating the one or more parallel fill shapes to the at least one shape based in part or in whole upon the one or more classes while automatically satisfying one or more design rules, and perform one or more post-layout operations on the layout including the one or more parallel fill shapes.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: May 16, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Alexandre Arkhipov, Giles V. Powell, Roland Ruehl, Karun Sharma
  • Patent number: 9646128
    Abstract: A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ashok Mehta, Stanley John, Kai-Yuan Ting, Sandeep Kumar Goel, Chao-Yang Yeh
  • Patent number: 9641001
    Abstract: An electronic apparatus includes a power receiving means for wirelessly receiving power, a detection means for detecting whether the electronic apparatus is in a predetermined state, a load means supplied with power from the power receiving means, and a control means that performs control so a second power is supplied from the power receiving means to the load means if the detection means detects that the electronic apparatus is in the predetermined state and a first power is supplied from the power receiving means to the load means, wherein the second power is lower than the first power, and the control means further performs control so the first power is supplied from the power receiving means to the load means if the detection means detects the electronic apparatus is in a state different from the predetermined state and the supplied power is reduced to a predetermined power value or less.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: May 2, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventor: Iori Aikawa
  • Patent number: 9634500
    Abstract: The storage battery system includes a storage battery comprising a plurality of battery modules; a plurality of voltage monitoring circuits for monitoring a voltage of the battery module; and a control device that controls charging and discharging of the storage battery on the basis of monitoring information that is obtained by carrying out communication with the voltage monitoring circuits, wherein the control device comprises a determination unit that calculates an estimated output voltage of the storage battery by using the monitoring information that is obtained from any one of the voltage monitoring circuits before occurrence of a communication failure in a case where the communication failure with any one of the voltage monitoring circuits occurs, and compares the estimated output voltage and an output voltage of the storage battery after occurrence of the communication failure to determine an abnormal site of the communication failure.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: April 25, 2017
    Assignee: KEIHIN CORPORATION
    Inventors: Seiji Kamata, Satomu Sasaki
  • Patent number: 9626465
    Abstract: Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: April 18, 2017
    Assignee: Imagination Technologies Limited
    Inventors: Iain Singleton, Ashish Darbari, John Alexander Osborne Netterville
  • Patent number: 9626467
    Abstract: The present invention provides a SOI MOS device modeling method. The SOI MOS device is one having a source-drain injection not reaching the bottom. The method comprises: a) establishing an overall model comprising a primary MOS device model simulating an SOI MOS device having the source-drain injection reaching the bottom, a source body PN junction bottom capacitance model simulating a source body PN junction bottom capacitance, and a drain body PN junction bottom capacitance model simulating a drain body PN junction bottom capacitance; and b) extracting parameters respectively for the primary MOS device model, the source body PN junction bottom capacitance model, and the drain body PN junction bottom capacitance model in the overall model. In the prior art, the source body junction bottom capacitance and the drain body junction bottom capacitance in the SOI MOS device having a source-drain injection not reaching the bottom affect the performances of the device.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: April 18, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Jianhui Bu, Jinshun Bi, Jiajun Luo, Zhengsheng Han
  • Patent number: 9620975
    Abstract: A battery characteristic converter comprises an interface to a battery and to an electronic device to be powered with energy supplied by the battery. The interface to the battery and the interface to the electronic device are connected using a bidirectional voltage ratio converter. The bidirectional voltage ratio converter is controlled so that the characteristics at the interface to the electronic device are adapted to the electronic device, independently of the battery characteristics. Energy may flow to the electronic device to power the electronic device or from the electronic device to the battery to charge the battery, depending on a comparison of the characteristics at the interfaces.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: April 11, 2017
    Assignee: Nokia Technologies Oy
    Inventors: Matti Juhani Naskali, Heikki Sakari Paananen
  • Patent number: 9619312
    Abstract: Embodiments relate to pre-silicon device testing using a persistent command table. An aspect includes receiving a value for a persistent command parameter from a user. Another aspect includes determining whether the value of the persistent command parameter is greater than zero. Another aspect includes based on determining whether the value of the persistent command parameter is greater than zero, selecting a number of commands equal to the value of the persistent command parameter from a regular command table of a driver of a device under test. Another aspect includes adding the selected commands to the persistent command table of the driver. Another aspect includes performing testing of the device under test via the driver using only commands that are in the persistent command table of the driver.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dean G. Bair, Rebecca M. Gott, Edward J. Kaminski, Jr., William J. Lewis, Chakrapani Rayadurgam
  • Patent number: 9613177
    Abstract: One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Lei Yuan, Soo Han Choi, Jongwook Kye, Harry J. Levinson
  • Patent number: 9612277
    Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Stanley John, Ashok Mehta, Sandeep Kumar Goel, Kai-Yuan Ting
  • Patent number: 9607684
    Abstract: A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noise margin curve for the circuit, wherein the second static noise margin curve is complementary to the first static noise margin curve, matching the set to a two-dimensional model of a cell, and predicting the condition in accordance with hardware characterization data corresponding to the cell.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Keunwoo Kim
  • Patent number: 9608457
    Abstract: A charging device for commonly charging multiple digital electronic devices has a housing, a charge control unit and multiple outlet strips. The charge control unit is mounted inside the housing and has multiple relays. The outlet strips are electrically connected to the charge control unit with each outlet strip electrically connected to one of the relays. A charging method corresponding to the charging device is performed by the charge control unit without the need of users' configuration during a charge cycle. The charge method automatically determines if the outlet strips can simultaneously supply power to charge during each charge schedule of the charge cycle. At least one outlet strip supplies power to charge during each charge schedule, and each outlet strip supplies power to charge once, thereby achieving optimization for the charging process with automatic determination and enhancing charging efficiency and users' operational convenience.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: March 28, 2017
    Assignee: Aver Information Inc.
    Inventors: Lien-Kai Chou, Chao-Hung Chang, Chi-Fa Hsu
  • Patent number: 9601477
    Abstract: Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage. Ones of the inactive spare functional circuit cells respectively includes a set of second electrically interconnected transistors configured to define a second logic component and a second power rail configured to carry the first supply voltage. The set of electrically interconnected transistors is interconnected through a second set of conductive lines formed in the first conductive layer. The set of second electrically interconnected transistors is electrically disconnected from the second power rail.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 21, 2017
    Assignee: Marvell World Trade Ltd.
    Inventors: Carol Pincu, Rami Rozenzvaig
  • Patent number: 9594861
    Abstract: An improved approach is provided to implement equivalency checking. A check is performed as to whether two designs are equivalent without needing to analyze their outputs on a cycle-by-cycle basis. Instead, the two designs are checked to see if they are equivalent on the transaction-level. This approach abstracts the timing delays between the two designs, which allows verification of data transportation and transformation between the designs.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: March 14, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Antonio Celso Caldeira, Jr., Lawrence Chunkhang Loh, Marcus Vinicius da Mata Gomes
  • Patent number: 9589893
    Abstract: A semiconductor device includes a semiconductor chip, which includes a substrate, a multilayer interconnect layer formed over the substrate, a first cell column disposed along an edge of the substrate in a plan view, the first cell column having a first I/O cell and a first power supply cell, second cell column disposed along the first cell column in plan view, the second cell column having a second I/O cell, a first pad supplying a first supply voltage to the first power supply cell, a first voltage supply wire disposed over the first cell column, a second voltage supply wire disposed over the second cell column, and a first connection wire crossing the first voltage supply wire and the second voltage supply wire.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: March 7, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masafumi Tomoda, Masayuki Tsukuda
  • Patent number: 9582278
    Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: February 28, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
  • Patent number: 9581997
    Abstract: Methods, computer systems, and servers are provided for navigating a vehicle automatically from a current location to a destination location with or without a human operator controlling primary navigation of the vehicle. One example method includes identifying a vehicle location and determining if the vehicle location is near a self-park location. The method accesses mapping data for the self-park location and receiving a request to initiate a self-park process for the vehicle. The method includes forwarding instructions to the vehicle to proceed with the self-park process. The self-park process acting to control the vehicle to automatically move from a current location to a destination location in the self-park location, and the current location and the destination location are updated dynamically as the current location of the vehicle changes and based on conditions of the destination location.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: February 28, 2017
    Inventors: Angel A. Penilla, Albert S. Penilla
  • Patent number: 9577450
    Abstract: A charger for a hand-held power tool includes a power source interface, a charger base and a charging cradle rotatably supported on the charger base. The rotatable charging cradle includes at least two charging output terminals electrically connected to the power source interface. A power tool system includes the charger and the hand-held power tool. A method of charging the power tool system includes contacting charging input terminals of the power tool with the charging output terminals, rotating the charging cradle and the power tool relative to the charging base and supplying charging current to at least one battery cell while the charging cradle and the power tool are allowed to freely swing relative to the charging base.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: February 21, 2017
    Assignee: MAKITA CORPORATION
    Inventors: Shuji Yoshikawa, Tatsuya Nagahama, Nobuyasu Furui, Hitoshi Suzuki, Masaaki Fukumoto, Takuya Umemura, Kosuke Ito
  • Patent number: 9577449
    Abstract: A wireless charging device for use in providing electrical power to one or more portable electronic devices is provided. The wireless charging device includes a transmission coil coupled to an electrical power source. The transmission coil selectively transmits power from the electrical power source to at least one receiving coil in a first portable electronic device of the one or more portable electronic devices. The wireless charging device also includes a positioning system coupled to the transmission coil. The positioning system is configured to selectively rotate said transmission coil about a first axis and about a second axis.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: February 21, 2017
    Assignee: Honda Motor Co., Ltd.
    Inventor: Andrew R. Hoover