Patents Examined by Thuan Du
  • Patent number: 8898497
    Abstract: Includes receiving, from a link partner, a message specifying a link partner receive wake time and resolving to the lesser of the received link partner receive wake time and a local transmit wake time.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: November 25, 2014
    Inventors: Aviad Wertheimer, Robert Hays
  • Patent number: 8892922
    Abstract: Techniques are disclosed relating to detecting a voltage change. In one embodiment, an integrated circuit may include a monitor circuit and a power management unit. The power management unit may be configured to request a voltage change. The monitor circuit may be configured to detect the requested voltage change and to provide an indication that the voltage change is complete. In response to the indication that the voltage change is complete, the power management unit may adjust a clock frequency.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: November 18, 2014
    Assignee: Apple Inc.
    Inventor: Michael Frank
  • Patent number: 8886988
    Abstract: In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock signal, and a test data signal is provided by adjusting the phase of the data signal. By latching the test data signal according to the test clock signal, a latched data may be acquired for determining an optimized phase relationship corresponding to the clock lane and the data lane. When transmitting the clock signal and the data signal in normal mode, the signal delays of the clock lane and the data lane may be adjusted according to the optimized phase relationship.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: November 11, 2014
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Ching-Chun Lin, Chih-Wei Tang, Hsueh-Yi Lee, Yu-Hsun Peng
  • Patent number: 8868897
    Abstract: A method and apparatus for self-monitoring to identify an occurrence of a threshold and rebooting in response to the occurrence of the threshold is provided. In an embodiment, a data processing apparatus comprises one or more processors; logic coupled to the one or more processors and comprising one or more stored sequences of instructions which, when executed by one or more processors, cause the one or more processors to obtain a threshold associated with the apparatus; self-monitor the apparatus to identify an occurrence of the threshold; and self-reboot the apparatus responsive to the occurrence of the threshold.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: October 21, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Alexander Clemm, Junekang Yang, Steve Chen-Lin Chang, Jiabin Zhao, Shyyunn Sheran Lin
  • Patent number: 8862920
    Abstract: A method of regulating power states in a processing system may begin with a processor component reporting a present processor power state to an input-output hub, where the present processor power state corresponds to one of a plurality of different processor power states ranging from an active state to an inactive state. The input-output hub receives data indicative of the present processor power state and, in response to receiving the present processor power state, establishes a lowest allowable hub power state that corresponds to one of a plurality of different hub power states ranging from an active state to an inactive state. The method continues by determining a present hub power state for the input-output hub, wherein depth of the present hub power state is less than or equal to depth of the lowest allowable hub power state.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 14, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander Branover, Maurice B. Steinman
  • Patent number: 8850249
    Abstract: In one embodiment, the present invention includes a method for receiving an information packet in a first port from an interconnect while an agent associated with the first port is in an idle low power state, transmitting a first signal from the first port along the interconnect to request re-transmission of the information packet, and sending a second signal from the first port to the agent to cause the agent to enter a fully active power state. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Eric Dahlen, Jimbo Alexander, Parthipan Satchi
  • Patent number: 8850172
    Abstract: Techniques for conducting an automated analysis of operations carried out during the critical path for a usage scenario and suggesting ways in which the configuration of the computing device could be changed to affect performance of the computing device. Computing devices can be operated in a variety of usage scenarios and users may notice the performance of a computing device in certain usage scenarios more particularly. Critical path analysis of operations conducted in these usage scenarios can be used to identify a critical path of the usage scenario, from which changes that could be made to the computing device to affect performance could be identified. Once the changes that could be made are identified, suggestions can be made to the user, such that a user is able to make changes to the configuration to affect performance when the user has little knowledge about how to improve configurations.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: September 30, 2014
    Assignee: Microsoft Corporation
    Inventors: Aaron Dietrich, Sylvain Goyette, Van Stephen Lanning
  • Patent number: 8832479
    Abstract: A mechanism is provided for scheduling application tasks. A scheduler receives a task that identifies a desired frequency and a desired maximum number of competing hardware threads. The scheduler determines whether a user preference designates either maximization of performance or minimization of energy consumption. Responsive to the user preference designating the performance, the scheduler determines whether there is an idle processor core in a plurality of processor cores available. Responsive to no idle processor being available, the scheduler identifies a subset of processor cores having a smallest load coefficient. From the subset of processor cores, the scheduler determines whether there is at least one processor core that matches desired parameters of the task. Responsive to at least one processor core matching the desired parameters of the task, the scheduler assigns the task to one of the at least one processor core that matches the desired parameters.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, Malcolm S. Ware
  • Patent number: 8832487
    Abstract: In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: September 9, 2014
    Assignee: Microsoft Corporation
    Inventor: Alan S. Fiedler
  • Patent number: 8832488
    Abstract: A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved through ports. The master counter is reloaded on rollover by a count limit register. The master counter has increment/decrement control and the rollover can be used in an interrupt control block to generate an interrupt request.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: September 9, 2014
    Assignee: Digi International Inc.
    Inventors: Norman L. Rogers, Monte J. Dalrymple, Lynn S. Wood, Steve J. Hardy
  • Patent number: 8826052
    Abstract: A mobile electronic communication device power management method and apparatus are disclosed for use in multiple processor hardware schemes having asymmetrical power demands between processors. Upon reaching an long duration idle state, a high-level processor with high power consumption requirements handling low-level system tasks updates a data set shared between processor subsystems containing information necessary to perform such low-level tasks. A proxy software module is initiated on a base-band processor with lower power consumption requirements. The proxy module accesses the shared data set and begins to control low-level system tasks, allowing the high-level processor to enter a dormant low power state. Upon the occurrence of a wake-up event, the high-level processor enters an active state. The shared data set is updated by the proxy software module and the proxy module is terminated. The high-level processor accesses the shared data set and resumes control of low-level system tasks.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: September 2, 2014
    Assignee: Marvell International Ltd.
    Inventors: Priya Vaidya, Moinul Khan
  • Patent number: 8812829
    Abstract: An information processing apparatus includes, a processer, a non-volatile memory to store a plurality of programs, a volatile memory to store at least one program executed by the processor and data accessed by the program, an acceptance unit to accept context information when power supplied to the processor is resumed from a state in which power supplied to the processor is interrupted while a power supplied to the volatile memory is maintained, a selection unit to select one program from the plurality of programs stored in the non-volatile memory based on context information accepted by the acceptance unit, and a program determination unit to determine whether the one program selected by the selection unit is stored in the volatile memory. When the processor determines the one program selected by the program determination unit is stored in the volatile memory, the processor starts the one program stored in the volatile memory.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Nimura, Zhaogong Guo, Kouichi Yasaki, Yousuke Nakamura
  • Patent number: 8788866
    Abstract: A method and system for reducing thermal load by monitoring and controlling current flow in a portable computing device (“PCD”) are disclosed. The method includes monitoring a temperature of the PCD and determining if the temperature has reached a temperature threshold condition. This temperature threshold condition may be comprised within any one or more of a plurality of thermal policy states, in which each thermal policy state may dictate various thermal mitigation techniques. The thermal policy states may be associated with values that may indicate thermal loading of a PCD. If the temperature has reached the first threshold condition, then electrical current exiting a power supply device may be monitored. If it is determined that the electrical current has exceeded a current threshold condition, such as a maximum current, a hardware device corresponding to the electrical current may be selected for application of a thermal mitigation technique.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: July 22, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jon James Anderson, Gary D. Good
  • Patent number: 8782448
    Abstract: According to one embodiment, a communication device includes a start-up signal reception unit that receives a start-up signal that a start node transmits for starting up a node to be started; a first interface connected to Ethernet; a second interface connected to Ethernet; a power reception unit that receives PoE power through the first interface; a PoE controller that receives the start-up signal and PoE power and gives a transmission instruction of a start-up power signal which is a PoE power signal having a signal pattern corresponding to the start-up signal; and a power transmission unit that receives the transmission instruction from the PoE controller and transmits the start-up power signal through the second interface.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshimichi Tanizawa, Takeshi Ishihara, Kotaro Ise, Eiji Kamagata, Yuichiro Oyama, Takaomi Murakami
  • Patent number: 8782460
    Abstract: An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network and a synchronous receiver disposed within a receiving device. The resistor network is configured to provide a ratio signal that indicates an amount to delay a data bit signal associated with a data group, where the data bit signal is transmitted by a transmitting device along with a data strobe signal. The synchronous receiver receives the data bit and the data strobe signals, and includes a delay-locked loop (DLL). The DLL is coupled to the ratio signal, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal, and where the delayed bit signal is delayed relative to the data strobe signal by the amount, thus allowing for proper reception of the data bit signal.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 15, 2014
    Assignee: VIA Technologies, Inc.
    Inventors: Darius D. Gaskins, James R. Lundberg
  • Patent number: 8775850
    Abstract: Some embodiments enable a first electronic device (e.g., a notebook computer) to obtain state information directly from another electronic device (e.g., a smartphone) so that the first electronic device may replicate a state of content of the other computing device. This is useful when a user of an electronic device desires to switch between one device and another device such that the user may continue an activity (e.g., playing a video game) on another device without having to restart the activity. This is also useful when a user of a first electronic device attempts to replicate the state of the activity on a second device from another user such that both users may participate in the same activity. In some embodiments, a user of a device may obtain content from a server and state information from another device to replicate the state of content on the other device.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: July 8, 2014
    Assignee: Amazon Technologies, Inc.
    Inventor: Steven Ka Cheung Moy
  • Patent number: 8775843
    Abstract: A central processing unit (CPU) can specify an initial (e.g., baseline) frequency for a clock signal used by a device to perform a task. The CPU is then placed in a reduced power mode. The device performs the task after the CPU is placed in the reduced power mode until a triggering event causes the device to send an interrupt to the CPU. In response to the interrupt, the CPU awakens to dynamically adjust the clock frequency. If the clock frequency is reset to the baseline value, then the CPU is again placed in the reduced power mode.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: July 8, 2014
    Assignee: NVIDIA Corporation
    Inventors: Aleksandr Frid, Parthasarathy Sriram
  • Patent number: 8762756
    Abstract: Power savings is provided to users of various electronic devices by monitoring the times and locations at which those users activate, deactivate, or otherwise change an operational state of one or more functional elements of a device. Other contextual or environmental information can be captured as well when the user performs such an action. One or more statistical analysis or prediction algorithms can be used to determine when and/or where the user is likely to repeat the one or more actions, where a confidence level of the prediction can be impacted at least in part by the environmental and contextual factors. When a prediction has a minimum level of confidence, a corresponding action can be performed automatically by the device when the relevant factors are met. Changes in behavior can be monitored such that the predictions can be refined over time.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: June 24, 2014
    Assignee: Amazon Technologies, Inc.
    Inventor: Steven Ka Cheung Moy
  • Patent number: 8756448
    Abstract: A computer system including at least one wake-up unit to sense whether a wake-up event occurs in a standby mode to decrease power consumption, a power supplying unit to supply power to the at least one wake-up unit, and a controlling unit to control a power supplying unit to the at least one wake-up unit in the standby mode according to predetermined setting corresponding to whether the at least one wake-up unit is operable.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: June 17, 2014
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventor: Kwang-hyun Kim
  • Patent number: 8751842
    Abstract: A microcontroller includes a data input unit that receives input data and outputs a start request signal according to the input data upon receiving the input data; an oscillator that starts according to the start request signal, to generate a clock signal; a clock signal supply control unit that outputs the start request signal supplied from the data input unit to the oscillator, and supplies the clock signal supplied from the oscillator generated after the start as a first clock signal and a second clock signal that are operation clock signals of the data input unit; and a CPU that operates the second clock signal as an operation clock, and performs processing according to the input data when the second clock signal is operated.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: June 10, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yosuke Kawanaka, Seiya Indo, Tomoya Katsuki, Shinichi Nakatsu, Kimiharu Eto, Hirotaka Shimoda, Kuniyasu Ishihara, Yuusuke Urakawa, Yuusuke Sakaguchi, Shingo Furuta