Abstract: In one aspect, the present disclosure relates to a method of de-duplicating data in a solid state storage device. The method can include receiving a block of data to be written to a solid state storage device, wherein the block of data comprises header portion and a payload, wherein the header portion comprises context information; and determining whether the payload should be de-duplicated prior to storage, based on the context information stored within the header portion; if the payload is determined to be de-duplicated, de-duplicating the payload; and storing the de-duplicated payload to the solid state storage device.

Abstract: One aspect of the current disclosure provides a method for utilizing a plurality of memories associated with a plurality of devices in a computer system. The method includes: 1) receiving a data set for executing an application employing the devices; 2) determining whether the data set is larger than a storage capacity of any of the memories; and 3) when the data set is larger than the storage capacity of any of the memories, replicating a portion of the data set across the memories and distributing a remaining portion of the data set across at least some of the memories.

Abstract: An alert configuration system facilitates accurate and reliable configuration of alerts for data protection policy in a data protection system, including eliminating or reducing manual configuration of data protection policy. The system identifies risks through trend analysis and behavioral statistics as applied to historical data, and automatically configures alerts for the identified risks so that alerts are generated upon detection of the identified risks. After detecting differences between tracked values for a data protection system and predicted values obtained through trend analysis and behavioral statistics as applied to the historical data, the alert configuration system automatically adjusts the configuration of alerts for data protection policy in accordance with the predicted values.

Abstract: A method for ensuring that a memory array such as a ferroelectric memory array is properly electrically connected. The method may be performed, for example, prior to a read or write cycle, during functional testing of the memory array, etc. In one implementation, the memory array is read and the data set including a data bit from each cell is stored in a register. A solid logic 0's pattern is written into the memory array, and each cell is read. If no cell returns a logic 1, it is determined that the memory array is properly connected and the register data values are written to the memory array. If one or more cells returns a logic 1, it is determined that the memory array is improperly connected, the register data values are written to the memory array, and the memory array is removed and reinstalled.

Abstract: Disclosed herein is a method and a system for handling read disturb errors in a memory unit. Status information related to each memory block in the memory unit is retrieved and plurality of target memory blocks with valid pages and having highest block erase count are identified for patrolling. Each valid page in the target memory blocks are patrolled for identifying read disturb errors. Finally, each valid page having read disturb errors are recycled, thereby effectively handling the read disturb errors in the memory unit. The method disclosed herein involves patrolling of only the valid pages in the memory block, thereby reducing the time required for handling the read disturb errors and improving the overall performance. Also, the method ensures data retention reliability within each memory blocks by patrolling the memory block in the order of highest block erase counts.

Abstract: Technologies for fine-grained completion tracking of memory buffer accesses include a compute device. The compute device is to establish multiple counter pairs for a memory buffer. Each counter pair includes a locally managed offset and a completion counter. The compute device is also to receive a request from a remote compute device to access the memory buffer, assign one of the counter pairs to the request, advance the locally managed offset of the assigned counter pair by the amount of data to be read or written, and advance the completion counter of the assigned counter pair as the data is read from or written to the memory buffer. Other embodiments are also described and claimed.

Abstract: Embodiments of the present invention provide methods and systems for calculating capacity allocation in storage systems. Embodiments of the present invention can be used to calculate a capabilities score for all storage systems, resulting in a list of storage systems, prioritized, so that a storage administrator may select automatically or manually, the best system to provision for the requesting application, based on the calculated capabilities score of each storage system.

Abstract: Persistent Memory, byte-addressable non-volatile memory technologies, offer performance advantages and access similar to Dynamic Random Access Memory while having the persistence of disk. Hardware Transactional Memory support, originally designed for DRAM concurrency control, can corrupt persistent memory transactions due to cache evictions before system failure. Unifying storage and memory on the main-memory bus and accessed directly while using HTM for concurrency control has previously required the additional burden of changes to processors to prevent possible data corruption. The present invention provides a solution for the durability of transactions to persistent memory while using HTM as a concurrency control mechanism, without any changes to processors or cache-coherency mechanisms. The invention includes a software only method and system that provides durability and ordering of HTM transactions to persistent memory.

Abstract: Systems and methods for performing application aware backups and/or generating other application aware secondary copies of virtual machines are described. For example, the systems and methods described herein may access a virtual machine, automatically discover various databases and/or applications (e.g., SQL, Exchange, Sharepoint, Oracle, and so on) running on the virtual machine, and perform data storage operations that generate a backup, or other secondary copy, of the virtual machine, as well as backups, or other secondary copies, of each of the discovered applications.

Abstract: A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising: a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and a coherency manager comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space; wherein the memory interface is configured to: receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space; translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus; receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and translate the snoop request, at the coherency manager, to a translated snoop request addr

Abstract: A method and associated system for randomizing data to be stored in a memory storage device including, receiving a plurality of data bytes to be randomized at a memory controller and written to a page of a memory storage device, wherein the page comprises a plurality of data sectors and wherein each of the plurality of data sectors are configured to store a plurality of data bytes, randomizing a first portion of the plurality of data bytes using a first randomizer initialized by a first seed to generate a first portion of randomized data bytes and randomizing a second portion of the plurality of data bytes using a second randomizer initialized by a second seed to generate a second portion of randomized data bytes, wherein the first seed is uncorrelated with the second seed.

Abstract: A system and method for optimization of non-volatile storage operational parameters is provided. The method may utilize a crowdsourcing server to gather performance data for multiple storage devices connected to respective remotely located host systems. The performance data may be transmitted at regular intervals or at predefined events and the crowdsourcing server may aggregate and determine improved operating parameters for each different type of storage device based on the data gathered for multiple instances of that type of storage device. The optimized operating parameters may be selected from pre-stored and pre-qualified operating parameter sets on the respective storage devices that the crowdsourcing server is aware of. The system includes a non-volatile memory and a controller that is configured to log performance data and transmit at least a portion of that logged data to the crowdsourcing server.

Abstract: The present disclosure, in various embodiments, describes technologies and techniques for use by a data storage controller or similar device for throttling the delivery of completion entries pertaining to the execution of commands by a nonvolatile memory (NVM) device, such as a NAND. In an illustrative example, the data storage controller selectively throttles the delivery of completion entries to a host processor using uniform delivery intervals to provide for the stable delivery of completion entries to the host. That is, in some examples, rather than immediately posting completion entries to a completion queue of the host using the same relative timing with which the completion entries are generated, the data storage controller selectively delays posting some completion entries relative to other completion entries, so the entries may be posted with uniform time delays. This may enable the host processor to more efficiently process the completion entries. NVMe examples are provided.

Abstract: Technologies for protecting virtual machine memory of a compute device include a virtual machine (VM) instantiated on the compute device, a virtual machine monitor (VMM) established on the compute device to control operation of the VM, a secured memory, and a memory manager. The memory manager receives a memory access request that includes a virtual linear address (LA) from the VM and performs a translation of the LA to a translated host physical address (HPA) of the compute device using one or more page tables associated with the VM and VMM. The memory manager determines whether a secured translation mapping of LA-to-HPA that corresponds to the LA is locked. If the mapping is locked, the memory manager verifies the translation based on a comparison of the translated HPA to a HPA translated using the secured translation mapping and, if verified, performs the memory access request using the translated HPA.

Abstract: A data processor comprises a memory-management-unit for receiving external-operation-data from a CPU. The memory-management-unit sets a deterministic-quantity value for the external-operation-data based on the external-operation-data. The deterministic-quantity value may be either an active-value or an inactive-value. The data processor has a non-deterministic-processor-block for receiving a memory-signal from the memory-management-unit, and has a control-block configured to (i) send the memory-signal to an NDP-output-terminal if the deterministic-quantity value is the active-value, thereby bypassing a performance-enhancement-block, or (ii) send at least a portion of the memory-signal that is representative of the request for response-data to the performance-enhancement-block if the deterministic-quantity value is the inactive-value.

Abstract: A system, according to one embodiment, includes: an automated data storage library which includes a designated physical mechanism accessible at the automated data storage library, and a memory. The automated data storage library is configured to capture a snapshot of one or more logs in response to the designated physical mechanism being triggered. The automated data storage library is also configured to store the snapshot in the memory. Other systems, methods, and computer program products are described in additional embodiments.

Abstract: The invention relates in particular to optimizing memory access in a microprocessor including several logic cores upon the resumption of executing a main application, and enabling the simultaneous execution of at least two processes in an environment including a hierarchically organized shared memory including a top portion and a bottom portion, a datum being copied from the bottom portion to the top portion for processing by the application. The computer is adapted to interrupt the execution of the main application. Upon an interruption in the execution of said application, a reference to a datum stored in a top portion of the memory is stored, wherein said datum must be used in order to enable the execution of the application. After programming a resumption of the execution of the application and before the resumption thereof, said datum is accessed in a bottom portion of the memory in accordance with the reference to be stored in a top portion of the memory.

Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

Abstract: Methods, systems, and apparatus, including an apparatus for accessing data. In some implementations, an apparatus includes address offset value elements that are each configured to store an address offset value. For each address offset value element, the apparatus can include address computation elements that each store a value used to determine the address offset value. One or more processors are configured to receive a program for performing computations using tensor elements of a tensor. The processor(s) can identify, in the program, a prologue or epilogue loop having a corresponding data array for storing values of the prologue or epilogue loop and populate, for a first address offset value element that corresponds to the prologue or epilogue loop, the address computation elements for the first address offset value element with respective values based at least on a number of iterations of the prologue or epilogue loop.

Abstract: A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory.