Abstract: The invention relates to an organic-based electronic component, especially a component with reduced pixel crosstalk. According to the invention, the crosstalk is reduced by a grid electrode.

Abstract: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a chip protection layer or an additional etching stop layer to cover conducting pads to prevent dicing residue from damaging or scratching the conducting pads. According to another embodiment, a chip protection layer, an additional etching stop layer formed thereon, or a metal etching stop layer level with conducting pads or combinations thereof may be used when etching an intermetal dielectric layer at a structural etching region and a silicon substrate to form an opening for subsequent semiconductor manufacturing processes.

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a base integrated circuit over the base substrate; attaching a lead to the base integrated circuit and the base substrate, the lead having a lead attachment portion over the base integrated circuit; and forming a base encapsulation over the lead, the base encapsulation having a cavity exposing the lead attachment portion.

Abstract: In semiconductor devices, the alignment mark for performing alignment processes of measurement tools and the like may be positioned within the die seal area on the basis of a geometric configuration, which still preserves mechanical integrity of the die seal without compromising the spatial information encoded into the alignment marks. For example, L-shaped alignment marks may be provided at one or more corners of the die seal area.

Abstract: A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about 2.0 ?m.

Abstract: An organic electroluminescent element comprising: a substrate; a pair of electrodes including an anode and a cathode, disposed on the substrate; and at least one organic layer including a light emitting layer, disposed between the electrodes. At least one of the organic layer contains a compound of general formula (1): A-(B)n-D, wherein A, D, and B represent groups of the following general formulas (2), (3), and (4) respectively; n represents 0 or 1; and when n is 0, A and D are not symmetrical about a point to each other, including the binding sites: wherein XA1 to XA11, XD1 to XD11, and XB1 to XB11 are as defined in the specification.

Abstract: Thermal conductivity in a stacked IC device can be improved by constructing one or more active temperature control devices within the stacked IC device. In one embodiment, the control devices are thermal electric (TE) devices, such as Peltier devices. The TE devices can then be selectively controlled to remove or add heat, as necessary, to maintain the stacked IC device within a defined temperature range. The active temperature control elements can be P-N junctions created in the stacked IC device and can serve to move the heat laterally and/or vertically, as desired.

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract: Embodiments of the present invention provide a bipolar transistor with low resistance base contact and method of manufacturing the same. The bipolar transistor includes an emitter, a collector, and an intrinsic base between the emitter and the collector. The intrinsic base extends laterally to an extrinsic base. The extrinsic base further includes a first semiconductor material with a first bandgap and a second semiconductor material with a second bandgap that is smaller than the first bandgap.

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract: A semiconductor device includes a plurality of functional element chips, an electric connection member joined to two of the functional element chips, a first wire and a resin configured to cover the functional element chips, the electric connection member and the first wire. One of the two functional element chips may be a first semiconductor chip having first and second major surface electrodes facing toward the same direction and a first rear surface electrode facing in a direction opposite to a direction in which the first major surface electrode faces. The electric connection member may be joined to the first major surface electrode. The first wire may be joined to the second major surface electrode. The first wire may include a portion overlapping with the electric connection member in a thickness direction of the first semiconductor chip.

Abstract: An imager device is disclosed including a first substrate having an array of photo-sensitive elements formed thereon, a first conductive layer formed above the first substrate, a first conductive member extending through the first substrate, the first conductive member being conductively coupled to the first conductive layer, a standoff structure formed above the first substrate, a second conductive layer formed above the standoff structure, the second conductive layer being conductively coupled to the first conductive layer, and an electrically powered device positioned above the standoff structure, the electrically powered device being electrically coupled to the second conductive layer.

Abstract: A semiconductor component includes a two-sided semiconductor body, an inner zone with a basic doping of a first conduction type, and two semiconductor zones. The first zone, disposed between the first side and inner zone, is of the first conduction type with a doping concentration higher than that of the inner zone. The second zone, disposed between the second side and inner zone, is of a second conduction type complementary to the first type with a doping concentration higher than that of the inner zone. At least one first edge chamfer extends at a first angle to the extension plane of the transition from the second zone to the inner zone at least along the edge of the second zone and inner zone. At least one buried zone of the second conduction type is provided between the first zone and inner zone, and extends substantially parallel to the first zone.

Abstract: There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.

Abstract: A semiconductor wafer contains semiconductor die separated by saw streets. The semiconductor wafer is singulated through a portion of the saw streets to form wafer sections each having multiple semiconductor die per wafer section attached by uncut saw streets. Each wafer section has at least two semiconductor die. The wafer sections are mounted over a temporary carrier in a grid pattern to reserve an interconnect area between the wafer sections. An encapsulant is deposited over the wafer sections and interconnect area. A conductive pillar can be formed in the encapsulant over the interconnect area. An interconnect structure is formed over the wafer sections and encapsulant in the interconnect area. The wafer sections and interconnect area are singulated to separate the semiconductor die each with a portion of the interconnect area. A heat sink or shielding layer can be formed over the wafer sections.

Abstract: In a manufacturing process of a semiconductor device formed using a thin film transistor, an object is to provide a technique by which the number of photomasks can be reduced, manufacturing cost can be reduced, and improvement in productivity and reliability can be achieved. A main point is that a film forming a channel protective layer is formed over an oxide semiconductor layer having a light-transmitting property, a positive photoresist is formed over the film forming a channel protective layer, and a channel protective layer is selectively formed over a channel formation region in the oxide semiconductor layer by using a back surface light exposure method.

Abstract: A semiconductor device includes a first contact in low Ohmic contact with a source region of the device and a first portion of a body region of the device formed in an active area of the device, and a second contact in low Ohmic contact with a second portion of the body region formed in a peripheral area of the device. The minimum width of the second contact at a first surface of the device is larger than the minimum width of the first contact at the first surface so that maximum current density during commutating the semiconductor device is reduced and thus the risk of device damage during hard commutating is also reduced.

Abstract: A semiconductor package includes a flexible base film having a first surface opposing a second surface, a semiconductor chip mounted on the first surface of the base film, and a touch sensing structure including at least one conductive pattern adjacent to the semiconductor chip. The at least one conductive pattern is disposed through the base film and has a surface exposed at the second surface of the base film. A contact condition of the semiconductor package is determined based on detection of a conductive path between the at least one conductive pattern and a conductive frame or support surface of the semiconductor package. The contact condition provides an indication of heat dissipation that may be expected to occur for the chip during operation.