Patents Examined by Tifney Skyles
  • Patent number: 8860179
    Abstract: The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: October 14, 2014
    Assignee: Fudan University
    Inventors: Pengfei Wang, Qingqing Sun, Wei Zhang
  • Patent number: 8853843
    Abstract: A semiconductor subassembly, a modular sidewall element having modular dimensions that accommodates placement of the semiconductor subassembly in a modular layout and a semiconductor substrate base element coupled to the modular sidewall element. The semiconductor substrate base element has at least one semiconductor element with a layout sized to be accommodated by modular dimensions of the modular sidewall element and the semiconductor substrate base element configured to form a base of the semiconductor subassembly.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: October 7, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Craig J. Rotay
  • Patent number: 8836127
    Abstract: An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Yu Lo, Bo-Jiun Lin, Hai-Ching Chen, Tien-I Bao, Shau-Lin Shue, Chen-Hua Yu
  • Patent number: 8836136
    Abstract: A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: September 16, 2014
    Assignee: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang, Zhijun Zhao
  • Patent number: 8802472
    Abstract: A pixel and a pixel array of an image sensor device of the present invention have small pixel sizes by resetting sensed charge using a diode built vertically above a substrate. The pixel and the pixel array also have low noise performance by using a JFET as a source follower transistor for sensing charge. The pixel includes a floating diffusion node configured to sense photo-generated charge, a reset diode configured to reset the floating diffusion node in response to a reset signal, and a junction field effect transistor configured to output a signal having an output voltage level corresponding to a charge level of the floating diffusion node.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Intellectual Ventures II LLC
    Inventor: Jaroslav Hynecek
  • Patent number: 8796846
    Abstract: A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: August 5, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Xusheng Bao, Kang Chen, Jianmin Fang
  • Patent number: 8796843
    Abstract: High-power and high-frequency semiconductor devices require high signal integrity and high thermal conductance assembly technologies and packages. In particular, wide-gap-semiconductor devices on diamond benefit from spatially separate electrical and thermal connections. This application discloses assembly and package architectures that offer high signal integrity and high thermal conductance.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: August 5, 2014
    Assignee: Element Six Technologies US Corporation
    Inventors: Dubravko I. Babic, Quentin E. Diduck, Alex Schreiber
  • Patent number: 8790945
    Abstract: A nitride semiconductor device includes a silicon substrate, a nitride semiconductor layer formed on the silicon substrate, and metal electrodes formed in contact with the silicon substrate. The metal electrodes has first metal layers which are formed in a shape of discrete islands and in contact with the silicon substrate, and second metal layers which are in contact with the silicon substrate exposed among the islands of the first metal layers and are formed to cover the first metal layers. Further, the second metal layers are made of a metal capable of forming ohmic contact with silicon, and the first metal layers are made of an alloy containing a metal and silicon, in which the metal is different than that in the second metal layer.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 29, 2014
    Assignee: Nichia Corporation
    Inventors: Kentaro Watanabe, Shunsuke Minato, Giichi Marutsuki
  • Patent number: 8779559
    Abstract: A semiconductor die including strain relief for through substrate vias (TSVs). The semiconductor die includes a semiconductor substrate having an active face. The semiconductor substrate includes conductive layers connected to the active face. The semiconductor die also includes a through substrate via extending only through the substrate. The through substrate via may include a substantially constant diameter through a length of the through substrate via. The through substrate via may be filled with a conductive filler material. The semiconductor die also includes an isolation layer surrounding the through substrate via. The isolation layer may include two portions: a recessed portion near the active face of the substrate capable of relieving stress from the conductive filler material, and a dielectric portion. A composition of the recessed portion may differ from the dielectric portion.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: July 15, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Vidhya Ramachandran, Shiqun Gu
  • Patent number: 8759901
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device including a semiconductor layer with a main surface, a first insulating layer formed on the main surface of the semiconductor layer, a charge storage layer formed on the first insulating layer, a second insulating layer formed on the charge storage layer, and a control gate electrode formed on the second insulating layer. At least one inelastic scattering film that reduces energy of electrons by scattering is contained in at least one of the charge storage layer and second insulating layer.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Higuchi, Yoshio Ozawa, Katsuyuki Sekine, Ryota Fujitsuka
  • Patent number: 8741757
    Abstract: Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Vamsi K. Paruchuri
  • Patent number: 8736041
    Abstract: A power converter includes a plurality of semiconductor modules that have main body sections, each of the main body sections has a semiconductor element therein, and power terminals projected from the main body sections, and a plurality of bus bars that connect the power terminals of the semiconductor modules. At least one of the plurality of the bus bars are connecting bus bars which have a plurality of terminal connecting sections that connect the power terminals of the plurality of different semiconductor modules, and connecting sections that connect the terminal connecting sections. The entirety of each of the connecting bus bars is formed integrally. The terminal connecting sections and the connecting section of every connecting bus bar are provided alternately in the connecting bus bar, and disposed in substantially the same position in a projecting direction of the power terminals.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 27, 2014
    Assignee: Denso Corporation
    Inventor: Makoto Okamura
  • Patent number: 8731252
    Abstract: A storage unit stores data of a first image associated with a contrast-enhanced cardiac region. A specification unit specifies a specific region included in the cardiac region on the basis of a distribution of pixel values of the data of the first image. A setting unit contracts the specified specific region, and set an ROI to the contracted specific region. A calculation unit calculates an index concerning the set ROI. The index is associated with a function of the specific region.
    Type: Grant
    Filed: March 17, 2009
    Date of Patent: May 20, 2014
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Medical Systems Corporation
    Inventors: Kazumasa Arakita, Naoko Toyoshima, Yasuko Fujisawa
  • Patent number: 8704277
    Abstract: A backside illuminated sensor includes a semiconductor substrate having a front surface and a back surface and a plurality of pixels formed on the front surface of the semiconductor substrate. A dielectric layer is disposed above the front surface of the semiconductor substrate. The sensor further includes a plurality of array regions arranged according to the plurality of pixels. At least two of the array regions have a different radiation response characteristic from each other, such as the first array region having a greater junction depth than the second array region, or the first array region having a greater dopant concentration than the second array region.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Hsuan Hsu, Dun-Nian Yaung
  • Patent number: 8704250
    Abstract: The present invention relates to a nitride semiconductor light emitting device including: a first nitride semiconductor layer having a super lattice structure of AlGaN/n-GaN or AlGaN/GaN/n-GaN; an active layer formed on the first nitride semiconductor layer to emit light; a second nitride semiconductor layer formed on the active layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. According to the present invention, the crystallinity of the active layer is enhanced, and optical power and reliability are also enhanced.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: April 22, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee
  • Patent number: 8704268
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer. The emitting layer is provided between the n-type layer and the p-type layer, and includes a plurality of barrier layers and a plurality of well layers, being alternately stacked. The p-side barrier layer being closest to the p-type layer among the plurality of barrier layer includes a first layer and a second layer, containing group III elements. An In composition ratio in the group III elements of the second layer is higher than an In composition ratio in the group III elements of the first layer. An average In composition ratio of the p-side layer is higher than an average In composition ratio of an n-side barrier layer that is closest to the n-type layer among the plurality of barrier layers.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8692333
    Abstract: A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: April 8, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Huei Chen, You-Cheng Xiao, Jung-Hsuan Chen, Shao-Yu Chou
  • Patent number: 8680538
    Abstract: In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: March 25, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoichiro Tarui, Kenichi Ohtsuka, Naruhisa Miura, Yoshinori Matsuno, Masayuki Imaizumi
  • Patent number: 8682052
    Abstract: Methods and devices for correcting wear pattern defects in joints. The methods and devices described herein allow for the restoration of correcting abnormal biomechanical loading conditions in a joint brought on by wear pattern defects, and also can, in embodiments, permit correction of proper kinematic movement.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: March 25, 2014
    Assignee: ConforMIS, Inc.
    Inventors: Wolfgang Fitz, Raymond Bojarski, Philipp Lang
  • Patent number: 8658494
    Abstract: Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: February 25, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Kai Frohberg, Juergen Boemmels, Matthias Schaller, Sven Mueller