Abstract: A high speed intelligent network recorder for recording a plurality of flows of network data packets into and out of a computer network over a relevant data time window is disclosed. The high speed intelligent network recorder includes a printed circuit board; a high speed network switching device mounted to the printed circuit board; and an X column by Y row array of a plurality of intelligent hard drives with micro-computers mounted to the printed circuit board and coupled in parallel with the high speed network switching device.

Abstract: A system having a plurality of devices configured in a daisy chain network including a communication bus connecting the devices and adapted to exchange address-setting information. Each device includes an input pin adapted to receive via an input signal line different from the communication bus a signal comprising configuration information for configuring at least the device; a configuration handling unit adapted to detect a configuration mode and to configure the device according to the configuration information; an indicator adapted to indicate whether the configuration handling unit has finished configuring the device; an output pin adapted to forward the configuration information to the daisy chain network when the indicator indicates the configuration of the device is done; and a safety handling unit adapted to be operable in a safety handling mode when the indicator indicates the configuration of the device is done.

Abstract: Provided herein may be a memory controller and a method of operating the memory controller. The memory controller may include: a host interface layer configured to receive a request for a memory device from a host; a flash translation layer configured to generate a descriptor including a flag indicating whether the request is a priority read request; and a flash interface layer configured to suspend requests input prior to the priority read request depending on the flag, store the requests input prior to the priority read request, and perform the priority read request.

Abstract: A system and method for management of data and power of a data acquisition device may include a power and storage module (PSM) comprising a memory and a power source unit, the PSM adapted to provide power to a data acquisition portable device (DAPD) and to store data received from the DAPD and a docking unit adapted to charge the power source unit and to perform at least one of: reading information from the memory and writing information to the memory. Charging the power source unit and transferring data to/from the memory may be done substantially at the same time and by the same docking unit.

Abstract: An electronic device may include an applications processor that communicates with a peripheral input-output (I/O) device using a coprocessor. The applications processor may include a first interprocessor communications (IPC) module, whereas the coprocessor may include a second IPC module for interfacing with the first IPC module. The first IPC module may forward a group of transactions to a submission queue and may ring a submission doorbell interrupt to signal that work items are pending in the submission queue. In response, the second IPC module may dequeue the work items from the submission queue and process these items at the I/O device. The second IPC module may provide a group of completed transactions to a completion queue and may ring a completion doorbell interrupt to signal that items are pending in the completion queue. Thereafter, the completed items are forwarded to other parts of the applications processor for processing.

Abstract: Technologies for increasing the reporting granularity of media render data transfers includes determining an estimated amount of transferred media data transferred by a direct memory access (DMA) controller of a compute device to a render link based on an elapsed time since the initiation of the rendering process and a data transfer rate of the render link. In some embodiments, an error value indicative of a difference between the estimated amount of transferred media data and a reported amount of transferred media data by the DMA controller is determined. If the error value fails to satisfy a threshold error value, the estimated amount of transferred media data may be determined based on a mean error value of previously determined estimated amount of transferred media data.

Abstract: An apparatus and method for controlling a device with shared hardware resources to provide separate execution environments for control and data functions are disclosed. A processor may be configured to generate a first request to access control functions of the device in response to execution of a first thread, and generate a second request to access data functions of the device in response to execution of a second thread. A communication unit may send first indicative of the first request and second data indicative of the second request to the device via first and second ports, respectively.

Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, a plurality of slave devices electrically connected to the master device via the eSPI bus, and a first resistor. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. The first resistor is coupled between the alert handshake control line and a power supply. Each slave device obtains the number of slave devices according to a first voltage of the alert handshake control line.

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to assemble a general register file (GRF) message and hold the GRF message in storage in a data port until all data for the GRF message is received. Other embodiments are also disclosed and claimed.

Abstract: An information processing device includes a processor; and an offload circuit coupled to the processor via links, the offload circuit including: a first circuit that computes processes of applications, a second circuit that collects values indicating performance information of the links for flows corresponding to the processes of the applications and maximum values indicated in performance information and usable by the links, and a third circuit that determines a flow not satisfying requested performance information based on the values indicating the performance information of the links for the flows, selects a link to which the flow is to be allocated, based on the maximum values indicated in the performance information and usable by the links and values indicated in performance information and currently used by the links, and allocates the flow to the selected link.

Abstract: Interference cancellation in a receiver can be used to improve bandwidth efficiency. The transmission of bursts from different terminals scheduled at separate time intervals can overlap partially such that time used for information transmission is optimized. For example, a receiver includes a signal processor including instructions executable to select first data including a first burst and a successive second burst from a transmission. The signal processor demodulates and decodes information from the first burst. The signal processor further generates a remodulated first burst based on recoded and remodulated information and generates second data by subtracting the remodulated first burst from the first data. The signal processor synchronizes with a stored symbol pattern in the second burst; and demodulates and decodes the information from the second burst. With such arrangement, the performance of each link is not affected by the partially overlapping burst.

Abstract: Disclosed herein are system and electronic structure embodiments for implementing phase-aware control and scheduling. An embodiment includes a system with a bus controller configured to be activated in response to a first command. The bus controller may have a first clock speed and may drive an interface having a second clock speed. The system may further configure the bus controller to wait for a first time period in response to being activated, and a first circuit element structured to detect a first phase value of a first signal. In some embodiments, the bus controller may process a second command following passage of the first time period, and wait for a second time period, based on the detected first phase value and a ratio of the first and second clock speeds.

Abstract: According to one embodiment, a supervisory circuit includes a trigger determination circuit and a trigger table. The trigger determination circuit receives signal processing signals outputted from a plurality of signal processing circuits as trigger signals, determines whether processing operations by the signal processing circuits are executed in a predetermined order, and outputs an interrupt signal when detecting a trigger signal out of setting. The trigger table is provided with trigger-specific tables corresponding to the respective signal processing circuits, reads a trigger setting to occur next based on a trigger determined as being correct by the trigger determination circuit, and outputs a table read signal to the trigger determination circuit.

Abstract: One embodiment of the present invention discloses a configurable microcontroller unit (“CMU”) capable of providing one or more programmable input and output (“I/O”) interfaces. The CMU includes a processor, I/O ports, and programmable microcontroller (“PM”). The processor is configured to communicate with a host central processing unit (“CPU”) based on a set of predefined instruction code. The I/O ports are used to transmit information between the processor and an external device. The PM facilitates communication interfaces between the I/O ports and one or more external devices via one or more configurable communication standards selected by the PM in accordance with interface programming microcode.

Abstract: A device and method that include a power control analog subsystem of a universal serial bus (USB) compatible power supply device is disclosed. The power control analog subsystem includes a programmable reference generator to generate first reference voltages. The power control analog subsystem also includes multiplexers, where each of a plurality of multiplexers are coupled to a first terminal and a second terminal of a producer field-effect transistor (FET) to receive a first voltage (Vbus_in) and a second voltage (Vbus_c) and to output second reference voltages. The power control analog subsystem further includes comparators, wherein each of the comparators is coupled to receive a corresponding reference voltage of the first reference voltages from the programmable reference generator and to receive a corresponding selected voltage from a corresponding multiplexer of the multiplexers. Each of the comparators is configured to output a corresponding system interrupt based on a corresponding voltage condition.

Abstract: Problems such as an operation stop of a controller caused by leaving out a mismatch requiring a change can be prevented. When a setting value is changed in a unit operation setting, an allocation management part specifies a storage capacity required for a storage of input data based on the changed setting value, and judges whether a mismatch occurs in an allocation state between the input data and a storage area specified in an I/O allocation setting.

Abstract: A signature is generated to indicate a direct memory access (DMA) operation involving a transfer, by a DMA engine, of data between a host memory circuit and an endpoint memory circuit of an endpoint processor circuit. First descriptors of the DMA engine are defined relative to the endpoint memory circuit or host memory circuit. A signature is received that indicates that second descriptors have been configured by the endpoint processor circuit. In response to receiving the endpoint signature, the DMA engine is enabled to begin the DMA operation.

Abstract: A storage system provides a logical volume to a computer, manages the logical volume and a port receiving an I/O request for the logical volume in correspondence with each other, and holds assigned processor management information for managing correspondence between a processor for executing I/O processing based on an I/O request accumulated in a queue and an assigned port being a port corresponding to the queue. The processor identifies an assigned port on the basis of the assigned processor management information, executes I/O processing for the logical volume corresponding to the assigned port, and executes I/O processing on the basis of an I/O request received via the assigned port corresponding to another operation core.

Abstract: An operation method of an electronic system includes the following steps. When a first communication module of the electronic device receives a call signal, a controller of an electronic device detects whether an expansion device is electrically connected to the electronic device. Based on a result of the controller detecting whether the expansion device is electrically connected to the electronic device, it is determined whether the electronic system performs sound amplification with a first speaker of the electronic device or performs playing with a second speaker of the expansion device.

Abstract: In an embodiment, a system comprises: a first bus; a second bus; a first peripheral coupled to the first bus and the second bus, the first peripheral configured to receive a command from the first bus and to generate data in response to the first command; and a second peripheral coupled to the first bus and the second bus, the second peripheral configured to initiate transfer of the generated data from the first peripheral to the second peripheral over the second bus such that access to the generated data through the first bus is prevented.