Patents Examined by Timothy M. Speer
  • Patent number: 8206833
    Abstract: A metal oxide film suitable for protection of metals, composed mainly of aluminum. A metal oxide film includes a film of an oxide of a metal composed mainly of aluminum, having a thickness of 10 nm or greater, and exhibiting a moisture release rate from the film of 1E18 mol./cm2 or less. Further, there is provided a process for producing a metal oxide film, wherein a metal composed mainly of aluminum is subjected to anodic oxidation in a chemical solution of 4 to 10 pH value so as to obtain a metal oxide film.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: June 26, 2012
    Assignees: Tohoku University, Mitsubishi Chemical Corporation
    Inventors: Tadahiro Ohmi, Yasuyuki Shirai, Hitoshi Morinaga, Yasuhiro Kawase, Masafumi Kitano, Fumikazu Mizutani, Makoto Ishikawa
  • Patent number: 8071145
    Abstract: The present invention provides a food product comprising: a formed reduced glycemic response cereal component; and a non-sticky reduced glycemic response sweetener coating over the formed cereal component, the sweetener coating comprising: a first sticky layer comprising at least about 30% fructose (of the total sweetener coating); a second less sticky layer having a DE value of about 60 or less and comprising up to about 17% fructose and at least about 1% non-fructose carbohydrates (of the total sweetener coating); and third layer comprising crystalline fructose. The present invention also provides a process for forming the sweetener coating over the formed cereal component comprising the following steps: (a) providing a formed cereal component having thereon a first sticky layer comprising fructose; (b) forming over the first sticky layer a less stick second layer comprising non-fructose carbohydrates and optionally fructose; and (c) applying crystalline fructose over the second layer.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: December 6, 2011
    Assignee: Abbott Laboratories
    Inventors: Normanella T. DeWille, Judith R Atkinson, Neile K. Edens, Terrence B. Mazer, Kelley J. Lowe, Douglas J. Wearly, Allison Ogilvie
  • Patent number: 8062765
    Abstract: The inventors have conducted vigorous studies, and discovered as a result that it is possible to form a silver layer having a high reflectance of about 90 to 99% in a visible light area by setting a grain size of an outermost surface of a silver plated layer within a range of 0.5 ?m or more to 30 ?m or less.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: November 22, 2011
    Assignee: Panasonic Electric Works, Ltd.
    Inventors: Youichiro Nakahara, Naoto Ikegawa
  • Patent number: 8038857
    Abstract: Provided are a thin film transistor substrate having a transparent electroconductive film in which residues and so on resulting etching are hardly generated; a process for producing the same; and a liquid crystal display using this thin film transistor substrate. A thin film transistor substrate, comprising a transparent substrate, a source electrode formed over the transparent substrate, a drain electrode formed over the transparent substrate, and a transparent pixel electrode formed over the transparent substrate, wherein the transparent pixel electrode is a transparent electroconductive film which is made mainly of indium oxide, and further comprises one or two or more oxides selected from tungsten oxide, molybdenum oxide, nickel oxide and niobium oxide, and the transparent pixel electrode is electrically connected to the source electrode or the drain electrode; a process for producing the same; and a liquid crystal display using this thin film transistor substrate.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: October 18, 2011
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Kazuyoshi Inoue, Shigekazu Tomai, Masato Matsubara
  • Patent number: 8025991
    Abstract: By using the PVD process, cutting tools are provided with a coating that is a mono-phase ternary or more complex oxide. By appropriately defining the involved major component and minor component in terms of atom percent, the distortions of the formed oxide can be controlled in a specific manner and in order to influence the properties of said oxide. Alternatively, the layer may contain an amorphous oxide phase with oxide crystallites embedded therein. The oxide crystallites may be binary, ternary or more complex. One or more different types of crystallites may be present adjacent to each other.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: September 27, 2011
    Assignee: Walter AG
    Inventor: Veit Schier
  • Patent number: 8025980
    Abstract: The invention provides a hot dip galvanized steel sheet which has: a hot dip galvanizing layer having a flat part on a surface thereof; and a film formed on the flat part. The film is composed of a compound containing Zn, Fe, and O, having an average film thickness A in a range from 10 to 100 nm determined by an element analysis of the film, and has {[Fe]/([Zn]+[Fe])} in the film in a range from 0.002 to 0.25, where [Zn] and [Fe] designate the content (% by atom) of Zn and Fe in the film, respectively. Since the hot dip galvanized steel sheet of the invention has excellent press-formability, bondability, and phosphatability, it is suitable for automobiles and electrical appliances.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: September 27, 2011
    Assignee: JFE Steel Corporation
    Inventors: Shoichiro Taira, Yoshiharu Sugimoto, Yoichi Miyakawa, Akira Gamou, Masayasu Nagoshi, Takashi Kawano
  • Patent number: 8021742
    Abstract: A thermal barrier coating system is provided. The thermal barrier coating system may include a first layer of ceramic insulating material (21) (see FIG. 1) disposed on a substrate surface. The thermal barrier coating system may also include a second layer of ceramic insulating material (25) disposed on the first layer of ceramic insulating material. The second layer of ceramic insulating material may include one or more crack arrestors therein. A third layer of ceramic insulating material (26) is disposed on the second layer of ceramic insulating material. The third layer may be configured as a sacrificial layer to absorb mechanical shock generated in the event of a foreign object collision with the third layer. The one or more crack arrestors in the second layer can avoid propagation towards the first layer of one or more cracks that can form in the event of the foreign object collision with the third layer.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: September 20, 2011
    Assignee: Siemens Energy, Inc.
    Inventors: Elvira V. Anoshkina, Ramesh Subramanian
  • Patent number: 8017247
    Abstract: Self-cleaning aluminum alloy substrates and methods of making the same are disclosed. In one embodiment, a substrate is provided, the substrate including an aluminum alloy body, an anodic oxide zone having micropores within a surface of the aluminum alloy body, the anodic oxide zone being substantially impermeable to contaminants, and a photocatalytic film located on at least a portion of the anodic oxide zone, wherein the photocatalytic film comprises photocatalytically active semiconductor. In one embodiment, a method is provided, the method including the steps of forming an anodic oxide zone in at least a portion of an aluminum alloy base, forming a photocatalytic film, the photocatalytic film being located on the anodic oxide zone, and sealing the anodic oxide zone with a sealant, wherein, as sealed, the anodic oxide zone is substantially impermeable to contaminants.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: September 13, 2011
    Assignee: Alcoa Inc.
    Inventors: Albert L. Askin, Verne Bergstrom, Robert E. Bombalski, Paula L. Kolek, Nickolas C. Kotow, Marlene A. Thompson, Jean Ann Skiles, Luis F. Vega, James M. Marinelli, Daniel Serafin
  • Patent number: 8012594
    Abstract: A method of manufacturing a functional film by which the functional film formed on a film formation substrate can be easily peeled from the film formation substrate. The method includes the steps of: (a) forming a separation layer by using an inorganic material on a substrate containing a material having heat tolerance to a predetermined temperature; (b) forming a layer to be peeled containing a functional film, which is formed by using a functional material, on the separation layer; and (c) performing heat treatment on a structure containing the substrate, the separation layer and the layer to be peeled at the predetermined temperature so as to peel the layer to be peeled from the substrate or reducing bonding strength between the layer to be peeled and the substrate.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: September 6, 2011
    Assignee: Fujifilm Corporation
    Inventor: Yukio Sakashita
  • Patent number: 8012612
    Abstract: The present invention provides an interlayer for laminated glass which comprises at least one layer composed of an opaque ethylene-vinyl acetate copolymer resin composition or opaque polyvinyl acetal resin composition, and also provides the laminated glass using such interlayers. The interlayer for laminated glass and the laminated glass according to the present invention can offer excellent privacy protection.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: September 6, 2011
    Assignee: Sekisui Chemical Co., Ltd.
    Inventor: Tsuyoshi Hasegawa
  • Patent number: 8012592
    Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a semiconductor structure includes a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The semiconductor structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region, a monocrystalline silicon layer disposed over the insulating layer in the first region, and a second monocrystalline semiconductor layer disposed over at least a portion of the first monocrystalline semiconductor layer in a second region and absent from the first region. The second monocrystalline semiconductor layer has a lattice constant different from the lattice constant of relaxed silicon.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: September 6, 2011
    Assignee: Massachuesetts Institute of Technology
    Inventor: Eugene A. Fitzgerald
  • Patent number: 8007930
    Abstract: This invention relates to lead free, cadmium free, bismuth free low melting high durability glass and enamel compositions. The compositions comprise silica, zinc, titanium, and boron oxide based glass frits. The resulting compositions can be used to decorate and protect automotive, beverage, architectural, pharmaceutical and other glass substrates.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: August 30, 2011
    Assignee: Ferro Corporation
    Inventor: George E. Sakoske
  • Patent number: 8007929
    Abstract: A surface coated cutting tool having, on a surface of a substrate, a hard coating layer including at least an aluminum oxide layer, the surface having a rake face on a main face thereof and a flank on a side face thereof, wherein, when a value calculated by the following equation (I) is a texture coefficient TC of the (HKL) plane of the aluminum oxide layer, a ratio of a texture coefficient TCR on the rake face to a texture coefficient TCF on the flank, TCF/TCR, is in a range of 0.3 to 0.95. TC = I ? ( HKL ) / I O ? ( HKL ) 1 / 6 ? ? ? [ I ? ( hkl ) / I 0 ? ( hkl ) ] ( I ) where I(HKL), I0(HKL) and ?[I(hkl)/I0(hkl)] are as described in the specification.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: August 30, 2011
    Assignee: Kyocera Corporation
    Inventors: Hirotoshi Itoh, Takahito Tanibuchi
  • Patent number: 8007931
    Abstract: A perpendicular magnetic recording medium including: a substrate; a perpendicular magnetic recording layer disposed over the substrate; a soft magnetic underlayer disposed between the substrate and the perpendicular magnetic recording layer; a shunting layer disposed under the soft magnetic underlayer; and an isolation layer disposed between the soft magnetic underlayer and the shunting layer and providing magnetic isolation between the shunting layer and the other layers disposed over the shunting layer are provided. The shunting layer is magnetically separated from the other magnetic layers disposed over the shunting layer, and shunts a magnetic field generated by the magnetic domain walls of the soft magnetic underlayer such that the magnetic field cannot reach a magnetic head, thereby increasing a signal-to-noise ratio (SNR).
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: August 30, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoo-san Lee, Chee-kheng Lim, Hoon-sang Oh, Sok-hyun Kong
  • Patent number: 8007899
    Abstract: A segmented abradable ceramic coating comprises a bond coat layer, at least one segmented 7 weight percent yttria-stabilized zirconia layer disposed upon said bond coat layer, and at least one 12 weight percent yttria-stabilized zirconia layer disposed upon said at least one segmented 7 weight percent yttria-stabilized zirconia layer.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: August 30, 2011
    Assignee: United Technologies Corporation
    Inventors: Melvin Freling, Kevin W. Schlichting
  • Patent number: 8007914
    Abstract: A two layer LTO backside seal for a wafer. The two layer LTO backside seal includes a low stress LTO layer having a first major side and a second major side, the first major5 side of the low stress LTO layer adjacent to one major side of the wafer. The two layer LTO backside seal further includes a high stress LTO layer having a first major side and second major side, the first major side of the high stress LTO layer adjacent the second major side of the low stress LTO layer.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: August 30, 2011
    Assignee: Siltronic AG
    Inventors: Jin-Xing Li, Boon-Koon Ow
  • Patent number: RE49415
    Abstract: Cement-SCM blends employ particle packing principles to increase particle packing density and reduce interstitial spacing between the cement and SCM particles. Particle packing reduces the amount of water required to obtain a cement paste having a desired flow, lowers the water-cementitious material ratio (w/cm), and increases early and long-term strengths. This may be accomplished by providing a hydraulic cement fraction having a narrow PSD and at least one SCM fraction having a mean particle size that differs from the mean particle size of the narrow PSD cement by a multiple of 3.0 or more to yield a cement-SCM blend having a particle packing density of at least 57.0%.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: February 14, 2023
    Assignee: ROMAN CEMENT, LLC
    Inventors: John M. Guynn, Andrew S. Hansen
  • Patent number: RE49503
    Abstract: The present invention is a sample processing apparatus. The apparatus includes: a sample processing unit configured to process a sample; a display; a memory for storing an electronic manual for the sample processing apparatus; and a controller that is capable of showing a relevant part of the electronic manual on the display when a trouble has occurred in the sample processing unit, the relevant part of the electronic manual describing an operation procedure to deal with the trouble.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: April 25, 2023
    Assignee: SYSMEX CORPORATION
    Inventors: Keisuke Kuwano, Shunsuke Ariyoshi, Tomomi Sugiyama
  • Patent number: RE49603
    Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: August 8, 2023
    Assignee: GAN SYSTEMS INC.
    Inventors: Thomas Macelwee, Greg P. Klowak, Howard Tweddle
  • Patent number: RE49773
    Abstract: The present invention relates generally to compositions for use in biological and chemical separations, as well as other applications. More specifically, the present invention relates to hybrid felts fabricated from electrospun nanofibers with high permeance and high capacity. Such hybrid felts utilize derivatized cellulose, and at least one non-cellulose-based polymer that may be removed from the felt by subjecting it to moderately elevated temperatures and/or solvents capable of dissolving the non-cellulose-based polymer to leave behind a porous nanofiber felt having more uniform pore sizes and other enhanced properties when compared to single component nanofiber felts.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: January 2, 2024
    Assignee: NANOPAREIL, LLC
    Inventors: Todd J. Menkhaus, Hao Fong